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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-02 16:55:37 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-02 16:55:37 +0000 |
| commit | b9699c009df52abde18f9c95ff54414e99ff9922 (patch) | |
| tree | d78be723c055ba757efe37bb387e691ab0a7caad | |
| parent | 1c1aab99aeb8170471589538e8faa1bc39e379e2 (diff) | |
| download | bcm5719-llvm-b9699c009df52abde18f9c95ff54414e99ff9922.tar.gz bcm5719-llvm-b9699c009df52abde18f9c95ff54414e99ff9922.zip | |
AMDGPU/GlobalISel: InstrMapping for G_ZEXT
llvm-svn: 326589
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 20 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir | 31 |
2 files changed, 51 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 92a9a3a1783..b4ea462959a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -324,6 +324,26 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize); break; } + case AMDGPU::G_ZEXT: { + unsigned Dst = MI.getOperand(0).getReg(); + unsigned Src = MI.getOperand(1).getReg(); + unsigned DstSize = getSizeInBits(Dst, MRI, *TRI); + unsigned SrcSize = getSizeInBits(Src, MRI, *TRI); + unsigned SrcBank = getRegBankID(Src, MRI, *TRI, + SrcSize == 1 ? AMDGPU::SGPRRegBankID : + AMDGPU::VGPRRegBankID); + unsigned DstBank = SrcBank; + if (SrcSize == 1) { + if (SrcBank == AMDGPU::SGPRRegBankID) + DstBank = AMDGPU::VGPRRegBankID; + else + DstBank = AMDGPU::SGPRRegBankID; + } + + OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, DstSize); + OpdsMapping[1] = AMDGPU::getValueMapping(SrcBank, SrcSize); + break; + } case AMDGPU::G_FCMP: { unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir new file mode 100644 index 00000000000..e50fca6572c --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: zext_i32_to_i64_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: zext_i32_to_i64_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s64) = G_ZEXT [[COPY]](s32) + %0:_(s32) = COPY $sgpr0 + %1:_(s64) = G_ZEXT %0 +... + +--- +name: zext_i32_to_i64_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1 + ; CHECK-LABEL: name: zext_i32_to_i64_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[ZEXT:%[0-9]+]]:vgpr(s64) = G_ZEXT [[COPY]](s32) + %0:_(s32) = COPY $vgpr0 + %1:_(s64) = G_ZEXT %0 +... |
