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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-29 19:01:48 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-29 19:01:48 +0000 |
commit | b90fc9b3b48cb91ee5b21f8f16b9ef1e95dec63f (patch) | |
tree | 1a31a91e9a3d57529a2124bd627f86c07f9d6fb9 | |
parent | 092c4dd5b60462baaaaa8730ac8d0228d07edfa6 (diff) | |
download | bcm5719-llvm-b90fc9b3b48cb91ee5b21f8f16b9ef1e95dec63f.tar.gz bcm5719-llvm-b90fc9b3b48cb91ee5b21f8f16b9ef1e95dec63f.zip |
AMDGPU/R600: Fix fixups used for constant arrays
Fixes bug 29289
llvm-svn: 279986
-rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp | 1 | ||||
-rw-r--r-- | llvm/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll | 28 |
2 files changed, 29 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp index c807b76d449..2e02cbafd71 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -120,6 +120,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, case FK_Data_4: case FK_Data_8: case FK_PCRel_4: + case FK_SecRel_4: return Value; default: llvm_unreachable("unhandled fixup kind"); diff --git a/llvm/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll b/llvm/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll new file mode 100644 index 00000000000..d5bf9c88b78 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll @@ -0,0 +1,28 @@ +; RUN: llc -filetype=obj -march=r600 -mcpu=cypress -verify-machineinstrs < %s | llvm-readobj -relocations -symbols | FileCheck %s + +@arr = internal unnamed_addr addrspace(2) constant [4 x i32] [i32 4, i32 5, i32 6, i32 7], align 4 + +; CHECK: Relocations [ +; CHECK: Section (3) .rel.text { +; CHECK: 0x58 R_AMDGPU_ABS32 .text 0x0 +; CHECK: } +; CHECK: ] + +; CHECK: Symbol { +; CHECK: Name: arr (11) +; CHECK: Value: 0x70 +; CHECK: Size: 16 +; CHECK: Binding: Local (0x0) +; CHECK: Type: Object (0x1) +; CHECK: Other: 0 +; CHECK: Section: .text (0x2) +; CHECK: } +define amdgpu_kernel void @test_constant_array_fixup(i32 addrspace(1)* nocapture %out, i32 %idx) #0 { +entry: + %arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(2)* @arr, i32 0, i32 %idx + %val = load i32, i32 addrspace(2)* %arrayidx + store i32 %val, i32 addrspace(1)* %out, align 4 + ret void +} + +attributes #0 = { nounwind } |