summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorEvan Cheng <evan.cheng@apple.com>2008-07-22 20:42:56 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-07-22 20:42:56 +0000
commitb8ff223f26428e9499faa2eeaec8e55e0ef22d89 (patch)
tree5b2e34e28bbfdea84cac978a8b32eaed5ef76656
parent62fffef385017d32ba0f125bf54cb2574dbfb19b (diff)
downloadbcm5719-llvm-b8ff223f26428e9499faa2eeaec8e55e0ef22d89.tar.gz
bcm5719-llvm-b8ff223f26428e9499faa2eeaec8e55e0ef22d89.zip
Fix pr2566: incorrect assumption about bit_convert. It doesn't not have to output a vector value. Patch by Nicolas Capens!
llvm-svn: 53932
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp3
-rw-r--r--llvm/test/CodeGen/X86/2008-07-22-CombinerCrash.ll16
2 files changed, 18 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 726108a9976..19723ba1b60 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4953,7 +4953,8 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
// look though conversions that change things like v4f32 to v2f64.
if (V->getOpcode() == ISD::BIT_CONVERT) {
SDOperand ConvInput = V->getOperand(0);
- if (ConvInput.getValueType().getVectorNumElements() == NumElts)
+ if (ConvInput.getValueType().isVector() &&
+ ConvInput.getValueType().getVectorNumElements() == NumElts)
V = ConvInput.Val;
}
diff --git a/llvm/test/CodeGen/X86/2008-07-22-CombinerCrash.ll b/llvm/test/CodeGen/X86/2008-07-22-CombinerCrash.ll
new file mode 100644
index 00000000000..a18564f4f97
--- /dev/null
+++ b/llvm/test/CodeGen/X86/2008-07-22-CombinerCrash.ll
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; PR2566
+
+external global i16 ; <i16*>:0 [#uses=1]
+external global <4 x i16> ; <<4 x i16>*>:1 [#uses=1]
+
+declare void @abort()
+
+define void @t() nounwind {
+ load i16* @0 ; <i16>:1 [#uses=1]
+ zext i16 %1 to i64 ; <i64>:2 [#uses=1]
+ bitcast i64 %2 to <4 x i16> ; <<4 x i16>>:3 [#uses=1]
+ shufflevector <4 x i16> %3, <4 x i16> undef, <4 x i32> zeroinitializer ; <<4 x i16>>:4 [#uses=1]
+ store <4 x i16> %4, <4 x i16>* @1
+ ret void
+}
OpenPOWER on IntegriCloud