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authorCraig Topper <craig.topper@intel.com>2017-09-26 21:35:11 +0000
committerCraig Topper <craig.topper@intel.com>2017-09-26 21:35:11 +0000
commitb7e4c94c6cd362bb330a5a446dbf59d5196d4ff3 (patch)
treea26f74eea3317e2b9ad1d4c10284b4f5d7068ae3
parent7f0eeb428b0792bd11facd020028e9ed49078e85 (diff)
downloadbcm5719-llvm-b7e4c94c6cd362bb330a5a446dbf59d5196d4ff3.tar.gz
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[X86] Fix register class name in a comment. NFC
llvm-svn: 314250
-rw-r--r--llvm/lib/Target/X86/X86FastISel.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 89bfdf45e21..85aa944c465 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -1984,7 +1984,7 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) {
// instead to prevent AH references in a REX instruction.
//
// The current assumption of the fast register allocator is that isel
- // won't generate explicit references to the GPR8_NOREX registers. If
+ // won't generate explicit references to the GR8_NOREX registers. If
// the allocator and/or the backend get enhanced to be more robust in
// that regard, this can be, and should be, removed.
unsigned ResultReg = 0;
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