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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2014-08-21 10:31:37 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2014-08-21 10:31:37 +0000 |
| commit | b791ef21d2a11b9117abac5cc40ccae73a22c2a8 (patch) | |
| tree | 593d3494beab2d9980af15ac194d03343ce29a60 | |
| parent | cb4efc1028778b31ffb2401befa8a70640cc5dc4 (diff) | |
| download | bcm5719-llvm-b791ef21d2a11b9117abac5cc40ccae73a22c2a8.tar.gz bcm5719-llvm-b791ef21d2a11b9117abac5cc40ccae73a22c2a8.zip | |
X86: Turn redundant if into an assertion.
While there remove noop casts.
llvm-svn: 216168
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index b2f2562f25a..00d1e5cd270 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1843,9 +1843,7 @@ X86TargetLowering::findRepresentativeClass(MVT VT) const{ default: return TargetLowering::findRepresentativeClass(VT); case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: - RRC = Subtarget->is64Bit() ? - (const TargetRegisterClass*)&X86::GR64RegClass : - (const TargetRegisterClass*)&X86::GR32RegClass; + RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass; break; case MVT::x86mmx: RRC = &X86::VR64RegClass; @@ -10669,12 +10667,12 @@ static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && isa<ConstantSDNode>(N2)) { unsigned Opc; - if (VT == MVT::v8i16) + if (VT == MVT::v8i16) { Opc = X86ISD::PINSRW; - else if (VT == MVT::v16i8) - Opc = X86ISD::PINSRB; - else + } else { + assert(VT == MVT::v16i8); Opc = X86ISD::PINSRB; + } // Transform it so it match pinsr{b,w} which expects a GR32 as its second // argument. |
