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| author | Vedant Kumar <vsk@apple.com> | 2018-05-24 23:00:22 +0000 |
|---|---|---|
| committer | Vedant Kumar <vsk@apple.com> | 2018-05-24 23:00:22 +0000 |
| commit | b70e35686b18a23d7fffa3060ef37a2279306155 (patch) | |
| tree | f20148a73a5cceed874a6fff47b20d60e54c4e11 | |
| parent | 40399a213d3c494933bd903bb02dba5c1f574363 (diff) | |
| download | bcm5719-llvm-b70e35686b18a23d7fffa3060ef37a2279306155.tar.gz bcm5719-llvm-b70e35686b18a23d7fffa3060ef37a2279306155.zip | |
[Debugify] Avoid printing unnecessary square braces, NFC
llvm-svn: 333236
| -rw-r--r-- | llvm/test/DebugInfo/debugify.ll | 4 | ||||
| -rw-r--r-- | llvm/test/Transforms/Mem2Reg/PromoteMemToRegister.ll | 2 | ||||
| -rw-r--r-- | llvm/tools/opt/Debugify.cpp | 6 |
3 files changed, 7 insertions, 5 deletions
diff --git a/llvm/test/DebugInfo/debugify.ll b/llvm/test/DebugInfo/debugify.ll index fd265378a4e..91e2371e16a 100644 --- a/llvm/test/DebugInfo/debugify.ll +++ b/llvm/test/DebugInfo/debugify.ll @@ -84,6 +84,6 @@ define weak_odr zeroext i1 @baz() { ; CHECK-FAIL: WARNING: Missing line 3 ; CHECK-FAIL: WARNING: Missing line 4 ; CHECK-FAIL: ERROR: Missing variable 1 -; CHECK-FAIL: CheckModuleDebugify [{{.*}}]: FAIL +; CHECK-FAIL: CheckModuleDebugify: FAIL -; PASS: CheckModuleDebugify [{{.*}}]: PASS +; PASS: CheckModuleDebugify: PASS diff --git a/llvm/test/Transforms/Mem2Reg/PromoteMemToRegister.ll b/llvm/test/Transforms/Mem2Reg/PromoteMemToRegister.ll index 08221907596..202b206d749 100644 --- a/llvm/test/Transforms/Mem2Reg/PromoteMemToRegister.ll +++ b/llvm/test/Transforms/Mem2Reg/PromoteMemToRegister.ll @@ -2,7 +2,7 @@ ; RUN: opt < %s -debugify -mem2reg -check-debugify -S 2>&1 | FileCheck %s ; CHECK-NOT: alloca -; CHECK: CheckModuleDebugify [{{.*}}]: PASS +; CHECK: CheckModuleDebugify: PASS define double @testfunc(i32 %i, double %j) { %I = alloca i32 ; <i32*> [#uses=4] diff --git a/llvm/tools/opt/Debugify.cpp b/llvm/tools/opt/Debugify.cpp index 39bbaa81316..fb810da231f 100644 --- a/llvm/tools/opt/Debugify.cpp +++ b/llvm/tools/opt/Debugify.cpp @@ -191,8 +191,10 @@ bool checkDebugifyMetadata(Module &M, errs() << "ERROR: Missing variable " << Idx + 1 << "\n"; HasErrors |= MissingVars.count() > 0; - errs() << Banner << " [" << NameOfWrappedPass << "]: " - << (HasErrors ? "FAIL" : "PASS") << '\n'; + errs() << Banner; + if (!NameOfWrappedPass.empty()) + errs() << " [" << NameOfWrappedPass << "]"; + errs() << ": " << (HasErrors ? "FAIL" : "PASS") << '\n'; if (HasErrors) { errs() << "Module IR Dump\n"; M.print(errs(), nullptr, false); |
