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| author | Mark Murray <mark.murray@arm.com> | 2019-10-16 15:59:06 +0000 |
|---|---|---|
| committer | Mark Murray <mark.murray@arm.com> | 2019-10-16 15:59:06 +0000 |
| commit | b6dd1286217711a40a3d8f20366a5fdad6b8c7db (patch) | |
| tree | 48fa0659bebfb29b7ccf2c3bce31203caee0f50c | |
| parent | fe2d15b39bb5265015802e9492f8c3eab8442de3 (diff) | |
| download | bcm5719-llvm-b6dd1286217711a40a3d8f20366a5fdad6b8c7db.tar.gz bcm5719-llvm-b6dd1286217711a40a3d8f20366a5fdad6b8c7db.zip | |
[AArch64,Assembler] Compiler support for ID_MMFR5_EL1
Summary: Add read-only system register ID_MMFR5_EL1 and unit tests.
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69039
llvm-svn: 375010
4 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index da5a3a1e3b7..2493be41765 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -612,6 +612,7 @@ def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>; def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>; def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>; def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>; +def : ROSysReg<"ID_MMFR5_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b110>; // Trace registers // Op0 Op1 CRn CRm Op2 diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s index a0807eacd46..4c65b039890 100644 --- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s +++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s @@ -3581,6 +3581,7 @@ msr ID_MMFR2_EL1, x12 msr ID_MMFR3_EL1, x12 msr ID_MMFR4_EL1, x12 + msr ID_MMFR5_EL1, x12 msr ID_ISAR0_EL1, x12 msr ID_ISAR1_EL1, x12 msr ID_ISAR2_EL1, x12 @@ -3680,6 +3681,9 @@ // CHECK-ERROR-NEXT: msr ID_MMFR4_EL1, x12 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: expected writable system register or pstate +// CHECK-ERROR-NEXT: msr ID_MMFR5_EL1, x12 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: msr ID_ISAR0_EL1, x12 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: expected writable system register or pstate diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s index 0cb8e3eb207..6c0c16e3f78 100644 --- a/llvm/test/MC/AArch64/basic-a64-instructions.s +++ b/llvm/test/MC/AArch64/basic-a64-instructions.s @@ -4295,6 +4295,7 @@ _func: mrs x9, ID_MMFR2_EL1 mrs x9, ID_MMFR3_EL1 mrs x9, ID_MMFR4_EL1 + mrs x9, ID_MMFR5_EL1 mrs x9, ID_ISAR0_EL1 mrs x9, ID_ISAR1_EL1 mrs x9, ID_ISAR2_EL1 @@ -4596,6 +4597,7 @@ _func: // CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} // encoding: [0xc9,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} // encoding: [0xe9,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr4_el1|ID_MMFR4_EL1}} // encoding: [0xc9,0x02,0x38,0xd5] +// CHECK: mrs x9, {{id_mmfr5_el1|ID_MMFR5_EL1}} // encoding: [0xc9,0x03,0x38,0xd5] // CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} // encoding: [0x09,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} // encoding: [0x29,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} // encoding: [0x49,0x02,0x38,0xd5] diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt index 482dd1f68ed..be1300aeba7 100644 --- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -3513,6 +3513,7 @@ # CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} # CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} # CHECK: mrs x9, {{id_mmfr4_el1|ID_MMFR4_EL1}} +# CHECK: mrs x9, {{id_mmfr5_el1|ID_MMFR5_EL1}} # CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} # CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} # CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} @@ -4069,6 +4070,7 @@ 0xc9 0x1 0x38 0xd5 0xe9 0x1 0x38 0xd5 0xc9 0x2 0x38 0xd5 +0xc9 0x3 0x38 0xd5 0x9 0x2 0x38 0xd5 0x29 0x2 0x38 0xd5 0x49 0x2 0x38 0xd5 |
