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| author | Chris Lattner <sabre@nondot.org> | 2004-12-15 23:38:13 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2004-12-15 23:38:13 +0000 |
| commit | b63ff380f14ff02567a61018678b595d7b07fa84 (patch) | |
| tree | ed095e4f13ac96ca23edadd9113999107004d16e | |
| parent | 298a7f8d8bee94e0398b362d88485ad8920c722c (diff) | |
| download | bcm5719-llvm-b63ff380f14ff02567a61018678b595d7b07fa84.tar.gz bcm5719-llvm-b63ff380f14ff02567a61018678b595d7b07fa84.zip | |
Make %'s a bit more explicit
llvm-svn: 18975
| -rw-r--r-- | llvm/Makefile.rules | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/llvm/Makefile.rules b/llvm/Makefile.rules index dbd23ecaec2..148188edbd2 100644 --- a/llvm/Makefile.rules +++ b/llvm/Makefile.rules @@ -938,43 +938,43 @@ INCFiles := $(filter %.inc,$(BUILT_SOURCES)) $(INCFiles) : $(TBLGEN) $(TDFiles) -%GenRegisterNames.inc : %.td +$(TARGET)GenRegisterNames.inc : $(TARGET).td $(Echo) "Building $(<F) register names with tblgen" $(Verb) $(TableGen) -gen-register-enums -o $@ $< -%GenRegisterInfo.h.inc : %.td +$(TARGET)GenRegisterInfo.h.inc : $(TARGET).td $(Echo) "Building $(<F) register information header with tblgen" $(Verb) $(TableGen) -gen-register-desc-header -o $@ $< -%GenRegisterInfo.inc : %.td +$(TARGET)GenRegisterInfo.inc : $(TARGET).td $(Echo) "Building $(<F) register info implementation with tblgen" $(Verb) $(TableGen) -gen-register-desc -o $@ $< -%GenInstrNames.inc : %.td +$(TARGET)GenInstrNames.inc : $(TARGET).td $(Echo) "Building $(<F) instruction names with tblgen" $(Verb) $(TableGen) -gen-instr-enums -o $@ $< -%GenInstrInfo.inc : %.td +$(TARGET)GenInstrInfo.inc : $(TARGET).td $(Echo) "Building $(<F) instruction information with tblgen" $(Verb) $(TableGen) -gen-instr-desc -o $@ $< -%GenAsmWriter.inc : %.td +$(TARGET)GenAsmWriter.inc : $(TARGET).td $(Echo) "Building $(<F) assembly writer with tblgen" $(Verb) $(TableGen) -gen-asm-writer -o $@ $< -%GenATTAsmWriter.inc : %.td +$(TARGET)GenATTAsmWriter.inc : $(TARGET).td $(Echo) "Building $(<F) AT&T assembly writer with tblgen" $(Verb) $(TableGen) -gen-asm-writer -o $@ $< -%GenIntelAsmWriter.inc : %.td +$(TARGET)GenIntelAsmWriter.inc : $(TARGET).td $(Echo) "Building $(<F) Intel assembly writer with tblgen" $(Verb) $(TableGen) -gen-asm-writer -asmwriternum=1 -o $@ $< -%GenInstrSelector.inc: %.td +$(TARGET)GenInstrSelector.inc: $(TARGET).td $(Echo) "Building $(<F) instruction selector with tblgen" $(Verb) $(TableGen) -gen-instr-selector -o $@ $< -%GenCodeEmitter.inc:: %.td +$(TARGET)GenCodeEmitter.inc: $(TARGET).td $(Echo) "Building $(<F) code emitter with tblgen" $(Verb) $(TableGen) -gen-emitter -o $@ $< |
