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authorCraig Topper <craig.topper@intel.com>2019-09-17 18:02:46 +0000
committerCraig Topper <craig.topper@intel.com>2019-09-17 18:02:46 +0000
commitb50894b9c369992c28f5669820bc7a1955aca947 (patch)
tree29995cd629ff5d997f9b8c8df06c5218232473dd
parenta1e29a3407fbb801a6a23e490f1bbf8a4167a5b8 (diff)
downloadbcm5719-llvm-b50894b9c369992c28f5669820bc7a1955aca947.tar.gz
bcm5719-llvm-b50894b9c369992c28f5669820bc7a1955aca947.zip
[X86] Simplify some code in LowerBUILD_VECTORvXi1. NFCI
The case were Immediate is 0 and HasConstElts is true should never happen since that would mean the constant elts were all zero. But we check for all zero build vector earlier. So just use HasConstElts and blindly take Immediate without checking if its 0. Move the code that bitcasts and extract the immediate into the the HasConstElts case since the other code just creates an undef with the right type. No casting needed. llvm-svn: 372153
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp23
1 files changed, 8 insertions, 15 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index b0c64a1bd8a..55024c38acd 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -8538,22 +8538,15 @@ static SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG,
// insert elements one by one
SDValue DstVec;
- SDValue Imm;
- if (Immediate) {
- MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
- Imm = DAG.getConstant(Immediate, dl, ImmVT);
- }
- else if (HasConstElts)
- Imm = DAG.getConstant(0, dl, VT);
- else
- Imm = DAG.getUNDEF(VT);
- if (Imm.getValueSizeInBits() == VT.getSizeInBits())
- DstVec = DAG.getBitcast(VT, Imm);
- else {
- SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
- DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
+ if (HasConstElts) {
+ MVT ImmVT = MVT::getIntegerVT(std::max(VT.getSizeInBits(), 8U));
+ SDValue Imm = DAG.getConstant(Immediate, dl, ImmVT);
+ MVT VecVT = VT.getSizeInBits() >= 8 ? VT : MVT::v8i1;
+ DstVec = DAG.getBitcast(VecVT, Imm);
+ DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, DstVec,
DAG.getIntPtrConstant(0, dl));
- }
+ } else
+ DstVec = DAG.getUNDEF(VT);
for (unsigned i = 0, e = NonConstIdx.size(); i != e; ++i) {
unsigned InsertIdx = NonConstIdx[i];
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