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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-02-25 16:44:35 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-02-25 16:44:35 +0000 |
| commit | b4548299814ef9d90e2ae99bb628c82c944234ea (patch) | |
| tree | ac57730f8521317bf1f06ed1485f36fbe68ee4d7 | |
| parent | 62e681744c4dbbb73d8f8200ad2777c02af3e66d (diff) | |
| download | bcm5719-llvm-b4548299814ef9d90e2ae99bb628c82c944234ea.tar.gz bcm5719-llvm-b4548299814ef9d90e2ae99bb628c82c944234ea.zip | |
Fix missing relocation for TLS addressing peephole optimization.
Report and fix due to Kai Nacke. Testcase update by me.
llvm-svn: 176029
| -rw-r--r-- | llvm/include/llvm/Support/ELF.h | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/tls.ll | 17 |
3 files changed, 15 insertions, 6 deletions
diff --git a/llvm/include/llvm/Support/ELF.h b/llvm/include/llvm/Support/ELF.h index bbd29553e35..8e6b91e00e3 100644 --- a/llvm/include/llvm/Support/ELF.h +++ b/llvm/include/llvm/Support/ELF.h @@ -483,6 +483,7 @@ enum { R_PPC64_TOC16_DS = 63, R_PPC64_TOC16_LO_DS = 64, R_PPC64_TLS = 67, + R_PPC64_TPREL16_LO = 70, R_PPC64_DTPREL16_LO = 75, R_PPC64_DTPREL16_HA = 77, R_PPC64_GOT_TLSGD16_LO = 80, diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp index ad41f3ad3a8..61868d446fe 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp @@ -153,6 +153,9 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target, case PPC::fixup_ppc_toc16: switch (Modifier) { default: llvm_unreachable("Unsupported Modifier"); + case MCSymbolRefExpr::VK_PPC_TPREL16_LO: + Type = ELF::R_PPC64_TPREL16_LO; + break; case MCSymbolRefExpr::VK_PPC_DTPREL16_LO: Type = ELF::R_PPC64_DTPREL16_LO; break; diff --git a/llvm/test/CodeGen/PowerPC/tls.ll b/llvm/test/CodeGen/PowerPC/tls.ll index 9021f03b9d8..151b4b7ddab 100644 --- a/llvm/test/CodeGen/PowerPC/tls.ll +++ b/llvm/test/CodeGen/PowerPC/tls.ll @@ -1,16 +1,21 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-freebsd10.0" -; RUN: llc -O0 < %s -march=ppc64 | FileCheck %s +; RUN: llc -O0 < %s -march=ppc64 | FileCheck -check-prefix=OPT0 %s +; RUN: llc -O1 < %s -march=ppc64 | FileCheck -check-prefix=OPT1 %s @a = thread_local global i32 0, align 4 -;CHECK: localexec: +;OPT0: localexec: +;OPT1: localexec: define i32 @localexec() nounwind { entry: -;CHECK: addis [[REG1:[0-9]+]], 13, a@tprel@ha -;CHECK-NEXT: li [[REG2:[0-9]+]], 42 -;CHECK-NEXT: addi [[REG1]], [[REG1]], a@tprel@l -;CHECK-NEXT: stw [[REG2]], 0([[REG1]]) +;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha +;OPT0-NEXT: li [[REG2:[0-9]+]], 42 +;OPT0-NEXT: addi [[REG1]], [[REG1]], a@tprel@l +;OPT0-NEXT: stw [[REG2]], 0([[REG1]]) +;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha +;OPT1-NEXT: li [[REG2:[0-9]+]], 42 +;OPT1-NEXT: stw [[REG2]], a@tprel@l([[REG1]]) store i32 42, i32* @a, align 4 ret i32 0 } |
