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| author | Craig Topper <craig.topper@intel.com> | 2017-12-27 22:25:59 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-27 22:25:59 +0000 |
| commit | b36447d346e99aa6f7b2d27093686d67c58013d3 (patch) | |
| tree | d4a79cf59d1e1c9800cfe260cf578fbb0f88d7c9 | |
| parent | 55cfa89f207aca571ca922a3e3f33056bcda17fb (diff) | |
| download | bcm5719-llvm-b36447d346e99aa6f7b2d27093686d67c58013d3.tar.gz bcm5719-llvm-b36447d346e99aa6f7b2d27093686d67c58013d3.zip | |
[X86] Enable avx512vpopcntdq and clwb for icelake.
Per table 1-1 of the October 2017 edition of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
llvm-svn: 321502
| -rw-r--r-- | clang/lib/Basic/Targets/X86.cpp | 3 | ||||
| -rw-r--r-- | clang/test/Preprocessor/predefined-arch-macros.c | 4 |
2 files changed, 6 insertions, 1 deletions
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 771d0c281ef..097d9178c68 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -132,13 +132,14 @@ bool X86TargetInfo::initFeatureMap( break; case CK_Icelake: - // TODO: Add icelake features here. setFeatureEnabledImpl(Features, "vaes", true); setFeatureEnabledImpl(Features, "gfni", true); setFeatureEnabledImpl(Features, "vpclmulqdq", true); setFeatureEnabledImpl(Features, "avx512bitalg", true); setFeatureEnabledImpl(Features, "avx512vnni", true); setFeatureEnabledImpl(Features, "avx512vbmi2", true); + setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); + setFeatureEnabledImpl(Features, "clwb", true); LLVM_FALLTHROUGH; case CK_Cannonlake: setFeatureEnabledImpl(Features, "avx512ifma", true); diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c index bd13daa441f..d2314d88e17 100644 --- a/clang/test/Preprocessor/predefined-arch-macros.c +++ b/clang/test/Preprocessor/predefined-arch-macros.c @@ -1060,10 +1060,12 @@ // CHECK_ICL_M32: #define __AVX512VBMI__ 1 // CHECK_ICL_M32: #define __AVX512VL__ 1 // CHECK_ICL_M32: #define __AVX512VNNI__ 1 +// CHECK_ICL_M32: #define __AVX512VPOPCNTDQ__ 1 // CHECK_ICL_M32: #define __AVX__ 1 // CHECK_ICL_M32: #define __BMI2__ 1 // CHECK_ICL_M32: #define __BMI__ 1 // CHECK_ICL_M32: #define __CLFLUSHOPT__ 1 +// CHECK_ICL_M32: #define __CLWB__ 1 // CHECK_ICL_M32: #define __F16C__ 1 // CHECK_ICL_M32: #define __FMA__ 1 // CHECK_ICL_M32: #define __GFNI__ 1 @@ -1111,10 +1113,12 @@ // CHECK_ICL_M64: #define __AVX512VBMI__ 1 // CHECK_ICL_M64: #define __AVX512VL__ 1 // CHECK_ICL_M64: #define __AVX512VNNI__ 1 +// CHECK_ICL_M64: #define __AVX512VPOPCNTDQ__ 1 // CHECK_ICL_M64: #define __AVX__ 1 // CHECK_ICL_M64: #define __BMI2__ 1 // CHECK_ICL_M64: #define __BMI__ 1 // CHECK_ICL_M64: #define __CLFLUSHOPT__ 1 +// CHECK_ICL_M64: #define __CLWB__ 1 // CHECK_ICL_M64: #define __F16C__ 1 // CHECK_ICL_M64: #define __FMA__ 1 // CHECK_ICL_M64: #define __GFNI__ 1 |
