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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-22 17:54:58 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-22 17:54:58 +0000 |
| commit | b362d0222988931a53bf8f0b320d65f5bdafd2de (patch) | |
| tree | aea33430e482297cd3e75107e3e4d961333d9652 | |
| parent | d7489a44dec063fdc60a331730e9284d53c7d798 (diff) | |
| download | bcm5719-llvm-b362d0222988931a53bf8f0b320d65f5bdafd2de.tar.gz bcm5719-llvm-b362d0222988931a53bf8f0b320d65f5bdafd2de.zip | |
[X86] Remove unnecessary CVT instrw overrides.
llvm-svn: 330552
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedBroadwell.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 9 |
3 files changed, 0 insertions, 13 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 2308ba50297..3903095ae67 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -1426,8 +1426,6 @@ def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm", "(V?)ADDSUBPDrm", "(V?)ADDSUBPSrm", "(V?)CVTDQ2PSrm", - "(V?)CVTPS2DQrm", - "(V?)CVTTPS2DQrm", "(V?)SUBPDrm", "(V?)SUBPSrm", "(V?)SUBSDrm", @@ -1551,7 +1549,6 @@ def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m", "VADDSUBPSYrm", "VCMPPDYrmi", "VCMPPSYrmi", - "VCVTDQ2PSYrm", "VCVTPS2DQYrm", "VCVTTPS2DQYrm", "VMAX(C?)PDYrm", diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index f5c635cd2a2..7aa834736d6 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -1493,7 +1493,6 @@ def: InstRW<[HWWriteResGroup52], (instregex "(V?)ADDPDrm", "(V?)ADDPSrm", "(V?)ADDSUBPDrm", "(V?)ADDSUBPSrm", - "(V?)CVTDQ2PSrm", "(V?)CVTPS2DQrm", "(V?)CVTTPS2DQrm", "(V?)SUBPDrm", diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index 20f10efad45..e0e89670067 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -1247,12 +1247,6 @@ def ZnWriteCVTPD2PSLd: SchedWriteRes<[ZnAGU,ZnFPU03]> { // x,m128. def : InstRW<[ZnWriteCVTPD2PSLd], (instregex "(V?)CVTPD2PS(X?)rm")>; -// x,y. -def ZnWriteCVTPD2PSYr : SchedWriteRes<[ZnFPU3]> { - let Latency = 5; -} -def : InstRW<[ZnWriteCVTPD2PSYr], (instregex "(V?)CVTPD2PSYrr")>; - // x,m256. def ZnWriteCVTPD2PSYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { let Latency = 11; @@ -1351,9 +1345,6 @@ def : InstRW<[ZnWriteCVTPS2PIr], (instregex "MMX_CVT(T?)PD2PIirr")>; def ZnWriteCVSTSI2SSr: SchedWriteRes<[ZnFPU3]> { let Latency = 5; } -// CVSTSI2SS. -// x,r32. -def : InstRW<[ZnWriteCVSTSI2SSr], (instregex "(V?)CVTSI2SS(64)?rr")>; // same as CVTPD2DQr // CVT(T)SS2SI. |
