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authorDaniel Sanders <daniel.sanders@imgtec.com>2015-03-16 13:54:19 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2015-03-16 13:54:19 +0000
commitb2d0c02451f458d51e9fda66701c68fa2f77ea11 (patch)
tree5ae6921b67ad9ad7bf4ec6c75151c5418698aa31
parentbf5b80f5f9a858a9550158a75d46bc0122739cd3 (diff)
downloadbcm5719-llvm-b2d0c02451f458d51e9fda66701c68fa2f77ea11.tar.gz
bcm5719-llvm-b2d0c02451f458d51e9fda66701c68fa2f77ea11.zip
[hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.
Summary: But still handle them the same way since I don't know how they differ on this target. No functional change intended. Reviewers: kparzysz, adasgupt Reviewed By: kparzysz, adasgupt Subscribers: colinl, llvm-commits Differential Revision: http://reviews.llvm.org/D8204 llvm-svn: 232374
-rw-r--r--llvm/include/llvm/IR/InlineAsm.h4
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp6
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLowering.h7
3 files changed, 10 insertions, 7 deletions
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index e94323a24d7..ea3708d4635 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -240,8 +240,8 @@ public:
// constraint codes for all targets.
Constraint_Unknown = 0,
Constraint_m,
- Constraint_o, // Unused at the moment since Constraint_m is always used.
- Constraint_v, // Unused at the moment since Constraint_m is always used.
+ Constraint_o,
+ Constraint_v,
Constraints_Max = Constraint_v,
Constraints_ShiftAmount = 16,
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 795faf97af4..d746df98cdc 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -1108,11 +1108,11 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
SDValue Inp = Op, Res;
switch (ConstraintID) {
- case InlineAsm::Constraint_o: // Offsetable.
- case InlineAsm::Constraint_v: // Not offsetable.
default:
return true;
- case InlineAsm::Constraint_m: // Memory.
+ case InlineAsm::Constraint_o: // Offsetable.
+ case InlineAsm::Constraint_v: // Not offsetable.
+ case InlineAsm::Constraint_m: // Memory.
if (SelectAddrFI(Inp, Res))
OutOps.push_back(Res);
else
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index 7b772f07eb0..99214c8d445 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -185,8 +185,11 @@ bool isPositiveHalfWord(SDNode *N);
unsigned getInlineAsmMemConstraint(
const std::string &ConstraintCode) const override {
- // FIXME: Map different constraints differently.
- return InlineAsm::Constraint_m;
+ if (ConstraintCode == "o")
+ return InlineAsm::Constraint_o;
+ else if (ConstraintCode == "v")
+ return InlineAsm::Constraint_v;
+ return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
// Intrinsics
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