summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorCraig Topper <craig.topper@intel.com>2019-08-13 00:00:27 +0000
committerCraig Topper <craig.topper@intel.com>2019-08-13 00:00:27 +0000
commitb2cff5e50f880df795db6c3dc382bf10014dd7a7 (patch)
tree708d7d4795a9711b48cae69048f4cf255b6b08f4
parent6817ce24c17261a8c9ec52d0dfd211ec89483962 (diff)
downloadbcm5719-llvm-b2cff5e50f880df795db6c3dc382bf10014dd7a7.tar.gz
bcm5719-llvm-b2cff5e50f880df795db6c3dc382bf10014dd7a7.zip
[X86] Remove 'Server' from Tigerlake description comments.
Tigerlake is a client CPU not a server CPU. llvm-svn: 368635
-rw-r--r--clang/include/clang/Basic/X86Target.def4
1 files changed, 2 insertions, 2 deletions
diff --git a/clang/include/clang/Basic/X86Target.def b/clang/include/clang/Basic/X86Target.def
index 7baacca6da8..ba4e5981e7d 100644
--- a/clang/include/clang/Basic/X86Target.def
+++ b/clang/include/clang/Basic/X86Target.def
@@ -173,8 +173,8 @@ PROC(IcelakeClient, "icelake-client", PROC_64_BIT)
/// Icelake server microarchitecture based processors.
PROC(IcelakeServer, "icelake-server", PROC_64_BIT)
-/// \name Tigerlake Server
-/// Tigerlake Server microarchitecture based processors.
+/// \name Tigerlake
+/// Tigerlake microarchitecture based processors.
PROC(Tigerlake, "tigerlake", PROC_64_BIT)
/// \name Knights Landing
OpenPOWER on IntegriCloud