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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2015-05-26 11:32:39 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2015-05-26 11:32:39 +0000 |
| commit | b2b901c607ae3149b6d3a0c53a45f22e3542fb04 (patch) | |
| tree | c40f13b5dfb15845eb08e3ded35222a0f557fb01 | |
| parent | 499292dedebdf38e9ead71f79eef67161689b0f2 (diff) | |
| download | bcm5719-llvm-b2b901c607ae3149b6d3a0c53a45f22e3542fb04.tar.gz bcm5719-llvm-b2b901c607ae3149b6d3a0c53a45f22e3542fb04.zip | |
AVX-512: fixed a bug in lowering VSELECT for 512-bit vector
https://llvm.org/bugs/show_bug.cgi?id=23634
llvm-svn: 238195
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/avx512-bugfix-23634.ll | 35 |
2 files changed, 36 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index ed9e1016e70..c85676e10dd 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -21710,7 +21710,7 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, // know will be matched by LowerVECTOR_SHUFFLEtoBlend. if ((N->getOpcode() == ISD::VSELECT || N->getOpcode() == X86ISD::SHRUNKBLEND) && - !DCI.isBeforeLegalize()) { + !DCI.isBeforeLegalize() && !VT.is512BitVector()) { SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget); if (Shuffle.getNode()) return Shuffle; diff --git a/llvm/test/CodeGen/X86/avx512-bugfix-23634.ll b/llvm/test/CodeGen/X86/avx512-bugfix-23634.ll new file mode 100644 index 00000000000..c31a13ad311 --- /dev/null +++ b/llvm/test/CodeGen/X86/avx512-bugfix-23634.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; CHECK-LABEL: f_fu +; CHECK-NOT: vpblend +; CHECK: vmovdqa32 {{.*}} {%k1} + +define void @f_fu(float* %ret, float* %aa, float %b) { +allocas: + %ptr_cast_for_load = bitcast float* %aa to <16 x float>* + %ptr_masked_load.39 = load <16 x float>, <16 x float>* %ptr_cast_for_load, align 4 + %b_load_to_int32 = fptosi float %b to i32 + %b_load_to_int32_broadcast_init = insertelement <16 x i32> undef, i32 %b_load_to_int32, i32 0 + %b_load_to_int32_broadcast = shufflevector <16 x i32> %b_load_to_int32_broadcast_init, <16 x i32> undef, <16 x i32> zeroinitializer + %b_to_int32 = fptosi float %b to i32 + %b_to_int32_broadcast_init = insertelement <16 x i32> undef, i32 %b_to_int32, i32 0 + %b_to_int32_broadcast = shufflevector <16 x i32> %b_to_int32_broadcast_init, <16 x i32> undef, <16 x i32> zeroinitializer + + %a_load_to_int32 = fptosi <16 x float> %ptr_masked_load.39 to <16 x i32> + %div_v019_load_ = sdiv <16 x i32> %b_to_int32_broadcast, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2> + + %v1.i = select <16 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>, <16 x i32> %a_load_to_int32 + + %foo_test = add <16 x i32> %div_v019_load_, %b_load_to_int32_broadcast + + + %add_struct_offset_y_struct_offset33_x = add <16 x i32> %foo_test, %v1.i + + %val = sitofp <16 x i32> %add_struct_offset_y_struct_offset33_x to <16 x float> + %ptrcast = bitcast float* %ret to <16 x float>* + store <16 x float> %val, <16 x float>* %ptrcast, align 4 + ret void +}
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