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authorRoman Gareev <gareevroman@gmail.com>2016-06-12 17:20:05 +0000
committerRoman Gareev <gareevroman@gmail.com>2016-06-12 17:20:05 +0000
commitb17b9a8324763a563bc03eafc8446fcf4c702491 (patch)
treea8761789238e5f0978193dab7e195c2ed2f0606a
parent071d0f180794f7819c44026815614ce8fa00a3bd (diff)
downloadbcm5719-llvm-b17b9a8324763a563bc03eafc8446fcf4c702491.tar.gz
bcm5719-llvm-b17b9a8324763a563bc03eafc8446fcf4c702491.zip
[NFC] Outline the application of register tiling.
llvm-svn: 272515
-rw-r--r--polly/include/polly/ScheduleOptimizer.h10
-rw-r--r--polly/lib/Transform/ScheduleOptimizer.cpp21
2 files changed, 24 insertions, 7 deletions
diff --git a/polly/include/polly/ScheduleOptimizer.h b/polly/include/polly/ScheduleOptimizer.h
index 10b2be5b5fb..4102e1571fd 100644
--- a/polly/include/polly/ScheduleOptimizer.h
+++ b/polly/include/polly/ScheduleOptimizer.h
@@ -90,6 +90,16 @@ private:
tileNode(__isl_take isl_schedule_node *Node, const char *Identifier,
llvm::ArrayRef<int> TileSizes, int DefaultTileSize);
+ /// @brief Tile a schedule node and unroll point loops.
+ ///
+ /// @param Node The node to register tile.
+ /// @param TileSizes A vector of tile sizes that should be used for
+ /// tiling.
+ /// @param DefaultTileSize A default tile size that is used for dimensions
+ static __isl_give isl_schedule_node *
+ applyRegisterTiling(__isl_take isl_schedule_node *Node,
+ llvm::ArrayRef<int> TileSizes, int DefaultTileSize);
+
/// @brief Check if this node is a band node we want to tile.
///
/// We look for innermost band nodes where individual dimensions are marked as
diff --git a/polly/lib/Transform/ScheduleOptimizer.cpp b/polly/lib/Transform/ScheduleOptimizer.cpp
index daaada2e557..cc8118bba7e 100644
--- a/polly/lib/Transform/ScheduleOptimizer.cpp
+++ b/polly/lib/Transform/ScheduleOptimizer.cpp
@@ -335,6 +335,17 @@ ScheduleTreeOptimizer::tileNode(__isl_take isl_schedule_node *Node,
return Node;
}
+__isl_give isl_schedule_node *
+ScheduleTreeOptimizer::applyRegisterTiling(__isl_take isl_schedule_node *Node,
+ llvm::ArrayRef<int> TileSizes,
+ int DefaultTileSize) {
+ auto *Ctx = isl_schedule_node_get_ctx(Node);
+ Node = tileNode(Node, "Register tiling", TileSizes, DefaultTileSize);
+ Node = isl_schedule_node_band_set_ast_build_options(
+ Node, isl_union_set_read_from_str(Ctx, "{unroll[x]}"));
+ return Node;
+}
+
bool ScheduleTreeOptimizer::isTileableBandNode(
__isl_keep isl_schedule_node *Node) {
if (isl_schedule_node_get_type(Node) != isl_schedule_node_band)
@@ -374,13 +385,9 @@ ScheduleTreeOptimizer::standardBandOpts(__isl_take isl_schedule_node *Node,
Node = tileNode(Node, "2nd level tiling", SecondLevelTileSizes,
SecondLevelDefaultTileSize);
- if (RegisterTiling) {
- auto *Ctx = isl_schedule_node_get_ctx(Node);
- Node = tileNode(Node, "Register tiling", RegisterTileSizes,
- RegisterDefaultTileSize);
- Node = isl_schedule_node_band_set_ast_build_options(
- Node, isl_union_set_read_from_str(Ctx, "{unroll[x]}"));
- }
+ if (RegisterTiling)
+ Node =
+ applyRegisterTiling(Node, RegisterTileSizes, RegisterDefaultTileSize);
if (PollyVectorizerChoice == VECTORIZER_NONE)
return Node;
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