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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-04 07:04:54 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-04 07:04:54 +0000 |
| commit | b0e32f1ba1742d1d355721ec3f1c2f48842bfa83 (patch) | |
| tree | 7c8d3792105c22429e4782c86aa5212e82dc4412 | |
| parent | 00bb5a99f58c9b64d10aa3f204e44d2d3b000b16 (diff) | |
| download | bcm5719-llvm-b0e32f1ba1742d1d355721ec3f1c2f48842bfa83.tar.gz bcm5719-llvm-b0e32f1ba1742d1d355721ec3f1c2f48842bfa83.zip | |
AMDGPU: Fix a slow test by using basic regalloc
This just tests that the register limit isn't exceeded,
so the regisetr allocation doesn't need to be great.'
The critically slow part is all in greedy RA, so
switch to basic.
llvm-svn: 277700
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/large-work-group-registers.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/large-work-group-registers.ll b/llvm/test/CodeGen/AMDGPU/large-work-group-registers.ll index 468633da56d..4463c193494 100644 --- a/llvm/test/CodeGen/AMDGPU/large-work-group-registers.ll +++ b/llvm/test/CodeGen/AMDGPU/large-work-group-registers.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=tonga -post-RA-scheduler=0 < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tonga -regalloc=basic -post-RA-scheduler=0 < %s | FileCheck %s ; CHECK: NumVgprs: 64 define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, <3 x i32> inreg, <3 x i32> inreg, <3 x i32>) #0 { |
