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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-10 03:22:20 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-10 03:22:20 +0000 |
| commit | b0df92577d6ed4a4d97fe85165d49ed33b6225b8 (patch) | |
| tree | 4ed9e55e522da3b3b30379267998f49c324d7120 | |
| parent | 3e3ddda7a250804abd3dfe84b95694c1ffea27e5 (diff) | |
| download | bcm5719-llvm-b0df92577d6ed4a4d97fe85165d49ed33b6225b8.tar.gz bcm5719-llvm-b0df92577d6ed4a4d97fe85165d49ed33b6225b8.zip | |
R600/SI: Add support for llvm.convert.{to|from}.fp16
llvm-svn: 212676
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/fp16_to_fp32.ll | 14 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/fp32_to_fp16.ll | 14 |
3 files changed, 34 insertions, 2 deletions
diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index 291d63455c9..b3b44e2b680 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -1078,8 +1078,12 @@ defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", [(set i32:$dst, (fp_to_sint f32:$src0))] >; defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; -////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; -//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; +defm V_CVT_F16_F32 : VOP1_32 <0x0000000a, "V_CVT_F16_F32", + [(set i32:$dst, (f32_to_f16 f32:$src0))] +>; +defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", + [(set f32:$dst, (f16_to_f32 i32:$src0))] +>; //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; diff --git a/llvm/test/CodeGen/R600/fp16_to_fp32.ll b/llvm/test/CodeGen/R600/fp16_to_fp32.ll new file mode 100644 index 00000000000..fa2e379ef7b --- /dev/null +++ b/llvm/test/CodeGen/R600/fp16_to_fp32.ll @@ -0,0 +1,14 @@ +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s + +declare i16 @llvm.convert.to.fp16(float) nounwind readnone + +; SI-LABEL: @test_convert_fp16_to_fp32: +; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]] +; SI: V_CVT_F16_F32_e32 [[RESULT:v[0-9]+]], [[VAL]] +; SI: BUFFER_STORE_SHORT [[RESULT]] +define void @test_convert_fp16_to_fp32(i16 addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { + %val = load float addrspace(1)* %in, align 4 + %cvt = call i16 @llvm.convert.to.fp16(float %val) nounwind readnone + store i16 %cvt, i16 addrspace(1)* %out, align 2 + ret void +} diff --git a/llvm/test/CodeGen/R600/fp32_to_fp16.ll b/llvm/test/CodeGen/R600/fp32_to_fp16.ll new file mode 100644 index 00000000000..9997cd3c08f --- /dev/null +++ b/llvm/test/CodeGen/R600/fp32_to_fp16.ll @@ -0,0 +1,14 @@ +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s + +declare float @llvm.convert.from.fp16(i16) nounwind readnone + +; SI-LABEL: @test_convert_fp16_to_fp32: +; SI: BUFFER_LOAD_USHORT [[VAL:v[0-9]+]] +; SI: V_CVT_F32_F16_e32 [[RESULT:v[0-9]+]], [[VAL]] +; SI: BUFFER_STORE_DWORD [[RESULT]] +define void @test_convert_fp16_to_fp32(float addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind { + %val = load i16 addrspace(1)* %in, align 2 + %cvt = call float @llvm.convert.from.fp16(i16 %val) nounwind readnone + store float %cvt, float addrspace(1)* %out, align 4 + ret void +} |
