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| author | Craig Topper <craig.topper@intel.com> | 2017-08-09 06:17:49 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-08-09 06:17:49 +0000 |
| commit | b049158a559ca1d7082b17af201f2a5d68a46c36 (patch) | |
| tree | dcc60e3a6bcdf6ca387206a5ba9426f01b67c036 | |
| parent | 5706c01c0bc47369507f4edcd6c605566eefa4d5 (diff) | |
| download | bcm5719-llvm-b049158a559ca1d7082b17af201f2a5d68a46c36.tar.gz bcm5719-llvm-b049158a559ca1d7082b17af201f2a5d68a46c36.zip | |
[X86] Add the rest of the ADC and SBB instructions to isDefConvertible.
I don't know if this really affects anything. Just thought it was weird that we had all of the ADD/SUB/AND/OR/XOR instructions.
llvm-svn: 310447
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 3a4876a9fc1..852b3d73a37 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -7113,16 +7113,20 @@ inline static bool isDefConvertible(MachineInstr &MI) { case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: + case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri: + case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8: + case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr: + case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm: + case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm: + case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri: + case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8: + case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr: + case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm: + case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm: case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r: case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1: case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1: case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1: - case X86::ADC32ri: case X86::ADC32ri8: - case X86::ADC32rr: case X86::ADC64ri32: - case X86::ADC64ri8: case X86::ADC64rr: - case X86::SBB32ri: case X86::SBB32ri8: - case X86::SBB32rr: case X86::SBB64ri32: - case X86::SBB64ri8: case X86::SBB64rr: case X86::ANDN32rr: case X86::ANDN32rm: case X86::ANDN64rr: case X86::ANDN64rm: case X86::BEXTR32rr: case X86::BEXTR64rr: |
