diff options
| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-13 13:08:38 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-13 13:08:38 +0000 |
| commit | af8b32e1766e9731027d9adb7a9195d356258704 (patch) | |
| tree | e85ac26bf4b0f0037ead3cef789b4ef32389fe1b | |
| parent | 86cb398b9d09148ef0bde14d6ed2136aa3b3097e (diff) | |
| download | bcm5719-llvm-af8b32e1766e9731027d9adb7a9195d356258704.tar.gz bcm5719-llvm-af8b32e1766e9731027d9adb7a9195d356258704.zip | |
[mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6
Summary:
These MIPS-3D instructions have never been implemented in LLVM so we only
add testcases.
Reviewers: zoran.jovanovic, jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4115
llvm-svn: 210899
| -rw-r--r-- | llvm/lib/Target/Mips/Mips32r6InstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s | 11 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s | 6 |
3 files changed, 16 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td index 2ed580e67ad..f2421418152 100644 --- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td @@ -25,7 +25,6 @@ include "Mips32r6InstrFormats.td" // Reencoded: sdbbp // Reencoded: sdc2 // Reencoded: swc2 -// Removed: bc1any2, bc1any4 // Rencoded: [ls][wd]c2 def brtarget21 : Operand<OtherVT> { diff --git a/llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s new file mode 100644 index 00000000000..99d10c327a4 --- /dev/null +++ b/llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s @@ -0,0 +1,11 @@ +# Instructions that are invalid but currently emit the wrong error message. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s index 6b980e6ed9a..4fc94e26eb1 100644 --- a/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s @@ -1,4 +1,4 @@ -# Instructions that are invalid +# Instructions that are invalid but currently emit the wrong error message. # # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ # RUN: 2>%t1 @@ -8,6 +8,10 @@ abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction |
