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| author | Tom Stellard <tstellar@redhat.com> | 2017-06-23 15:17:17 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2017-06-23 15:17:17 +0000 |
| commit | af552dc352d120dee5d8c20260403ee4197f32a2 (patch) | |
| tree | 6e3d6a8f2c109be8fab521309bb5fd1f4cae55e0 | |
| parent | a2af95a6154b05d05d2592ad6dac24269ad3d254 (diff) | |
| download | bcm5719-llvm-af552dc352d120dee5d8c20260403ee4197f32a2.tar.gz bcm5719-llvm-af552dc352d120dee5d8c20260403ee4197f32a2.zip | |
AMDGPU/GlobalISel: Mark 32-bit G_AND as legal
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D34349
llvm-svn: 306112
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir | 22 |
2 files changed, 23 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 58c025faffc..e30d510a350 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -36,6 +36,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() { const LLT P2 = LLT::pointer(2, 64); setAction({G_ADD, S32}, Legal); + setAction({G_AND, S32}, Legal); setAction({G_BITCAST, V2S16}, Legal); setAction({G_BITCAST, 1, S32}, Legal); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir new file mode 100644 index 00000000000..50ef150510d --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir @@ -0,0 +1,22 @@ +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- | + define void @test_and() { ret void } +... + +--- +name: test_and +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %vgpr0, %vgpr1 + ; CHECK-LABEL: name: test_and + ; CHECK: %2(s32) = G_AND %0, %1 + + %0(s32) = COPY %vgpr0 + %1(s32) = COPY %vgpr1 + %2(s32) = G_AND %0, %1 +... |
