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author | Thomas Lively <tlively@google.com> | 2018-08-28 18:49:47 +0000 |
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committer | Thomas Lively <tlively@google.com> | 2018-08-28 18:49:47 +0000 |
commit | adb6da10b81d35008178826adfc678275e776c9d (patch) | |
tree | 720368cb7c8633489860e9eb12a71eb6d2253d26 | |
parent | 88d99a09a2ff0ce63003bcad87250c814aa02a10 (diff) | |
download | bcm5719-llvm-adb6da10b81d35008178826adfc678275e776c9d.tar.gz bcm5719-llvm-adb6da10b81d35008178826adfc678275e776c9d.zip |
[WebAssembly][NFC] Document stackifier tablegen backend
Summary:
Add comments to help readers avoid having to read tablegen backends to
understand the code. Also remove unecessary breaks from the output.
Reviewers: dschuff, aheejin
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D51371
llvm-svn: 340864
-rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp | 9 | ||||
-rw-r--r-- | llvm/utils/TableGen/WebAssemblyStackifierEmitter.cpp | 13 |
2 files changed, 19 insertions, 3 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp index 0a58b9f47ac..3dca75dfefa 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp @@ -285,8 +285,13 @@ static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI) { static unsigned regInstructionToStackInstruction(unsigned OpCode) { // For most opcodes, this function could have been implemented as "return // OpCode + 1", but since table-gen alphabetically sorts them, this cannot be - // guaranteed (see e.g. BR and BR_IF), so we table-gen a giant switch - // statement instead. + // guaranteed (see e.g. BR and BR_IF). Instead we use a giant switch statement + // generated by a custom TableGen backend (WebAssemblyStackifierEmitter.cpp) + // that emits switch cases of the form + // + // case WebAssembly::RegisterInstr: return WebAssembly::StackInstr; + // + // for every pair of equivalent register and stack instructions. switch (OpCode) { default: llvm_unreachable( diff --git a/llvm/utils/TableGen/WebAssemblyStackifierEmitter.cpp b/llvm/utils/TableGen/WebAssemblyStackifierEmitter.cpp index de637e5be57..0b9741d22b8 100644 --- a/llvm/utils/TableGen/WebAssemblyStackifierEmitter.cpp +++ b/llvm/utils/TableGen/WebAssemblyStackifierEmitter.cpp @@ -17,6 +17,17 @@ namespace llvm { +// Find all register WebAssembly instructions and their corresponding stack +// instructions. For each pair, emit a switch case of the form +// +// case WebAssembly::RegisterInstr: return WebAssembly::StackInstr; +// +// For example, +// +// case WebAssembly::ADD_I32: return WebAssembly::ADD_I32_S; +// +// This is useful for converting instructions from their register form to their +// equivalent stack form. void EmitWebAssemblyStackifier(RecordKeeper &RK, raw_ostream &OS) { Record *InstrClass = RK.getClass("WebAssemblyInst"); for (auto &RecordPair : RK.getDefs()) { @@ -26,7 +37,7 @@ void EmitWebAssemblyStackifier(RecordKeeper &RK, raw_ostream &OS) { if (IsStackBased) continue; OS << " case WebAssembly::" << RecordPair.first << ": return " - << "WebAssembly::" << RecordPair.first << "_S; break;\n"; + << "WebAssembly::" << RecordPair.first << "_S;\n"; } } |