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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-30 21:32:10 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-30 21:32:10 +0000 |
| commit | ada6cf1b22d21f99ddb3781b7d00a80a98098a43 (patch) | |
| tree | 25590d1335f9e10c7b1b138072e757dda21fad19 | |
| parent | 41003af292ecb0807519eb29c9a25769110c40cb (diff) | |
| download | bcm5719-llvm-ada6cf1b22d21f99ddb3781b7d00a80a98098a43.tar.gz bcm5719-llvm-ada6cf1b22d21f99ddb3781b7d00a80a98098a43.zip | |
AMDGPU: Fix unused function
llvm-svn: 254333
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 05b54d0bae5..1b0cc87206f 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -542,11 +542,6 @@ SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, Align); // Alignment } -static ArrayRef<MCPhysReg> getAllSGPRs() { - return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), - AMDGPU::SGPR_32RegClass.getNumRegs()); -} - SDValue SITargetLowering::LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, |
