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| author | Hal Finkel <hfinkel@anl.gov> | 2014-03-27 21:26:33 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2014-03-27 21:26:33 +0000 |
| commit | ad801b74598514a2872b914eb4a28cdd27c9a90c (patch) | |
| tree | a368f652dcd5a967e7a2125c1bac7e86262e5cfc | |
| parent | 9dee449ee35746e64b7ea1df4a7eea82259476d0 (diff) | |
| download | bcm5719-llvm-ad801b74598514a2872b914eb4a28cdd27c9a90c.tar.gz bcm5719-llvm-ad801b74598514a2872b914eb4a28cdd27c9a90c.zip | |
[PowerPC] Expand v2i64 shifts
These operations need to be expanded during legalization so that isel does not
crash. In theory, we might be able to custom lower some of these. That,
however, would need to be follow-up work.
llvm-svn: 204963
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx.ll | 42 |
2 files changed, 46 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 6f640183f93..16ff0eb7d72 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -581,6 +581,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setOperationAction(ISD::ADD, MVT::v2i64, Expand); setOperationAction(ISD::SUB, MVT::v2i64, Expand); + setOperationAction(ISD::SHL, MVT::v2i64, Expand); + setOperationAction(ISD::SRA, MVT::v2i64, Expand); + setOperationAction(ISD::SRL, MVT::v2i64, Expand); + setOperationAction(ISD::LOAD, MVT::v2i64, Promote); AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64); setOperationAction(ISD::STORE, MVT::v2i64, Promote); diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll index 2524251a20a..89499560b34 100644 --- a/llvm/test/CodeGen/PowerPC/vsx.ll +++ b/llvm/test/CodeGen/PowerPC/vsx.ll @@ -487,3 +487,45 @@ define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) { ; CHECK: blr } +define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) { + %v = shl <2 x i64> %a, %b + ret <2 x i64> %v + +; CHECK-LABEL: @test60 +; This should scalarize, and the current code quality is not good. +; CHECK: stxvd2x +; CHECK: stxvd2x +; CHECK: sld +; CHECK: sld +; CHECK: lxvd2x +; CHECK: blr +} + +define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) { + %v = lshr <2 x i64> %a, %b + ret <2 x i64> %v + +; CHECK-LABEL: @test61 +; This should scalarize, and the current code quality is not good. +; CHECK: stxvd2x +; CHECK: stxvd2x +; CHECK: srd +; CHECK: srd +; CHECK: lxvd2x +; CHECK: blr +} + +define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) { + %v = ashr <2 x i64> %a, %b + ret <2 x i64> %v + +; CHECK-LABEL: @test62 +; This should scalarize, and the current code quality is not good. +; CHECK: stxvd2x +; CHECK: stxvd2x +; CHECK: srad +; CHECK: srad +; CHECK: lxvd2x +; CHECK: blr +} + |
