summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSimon Pilgrim <llvm-dev@redking.me.uk>2019-08-31 15:01:03 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2019-08-31 15:01:03 +0000
commitad020c0af15d9f9f61d8570a469d8efdd54a7acc (patch)
treee4216b4532d12770cc774a33d5d50cfaceef55b2
parentafcb3de117265a69d21e5673356e925a454d7d02 (diff)
downloadbcm5719-llvm-ad020c0af15d9f9f61d8570a469d8efdd54a7acc.tar.gz
bcm5719-llvm-ad020c0af15d9f9f61d8570a469d8efdd54a7acc.zip
Fix shadow variable warning. NFCI.
llvm-svn: 370585
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c61768c5b3b..9a36459cfe2 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -31109,8 +31109,8 @@ X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
DefRegs[MOp.getReg()] = true;
MachineInstrBuilder MIB(*MF, &II);
- for (unsigned RI = 0; SavedRegs[RI]; ++RI) {
- unsigned Reg = SavedRegs[RI];
+ for (unsigned RegIdx = 0; SavedRegs[RegIdx]; ++RegIdx) {
+ unsigned Reg = SavedRegs[RegIdx];
if (!DefRegs[Reg])
MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
}
OpenPOWER on IntegriCloud