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| author | Owen Anderson <resistor@mac.com> | 2011-08-22 18:22:06 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-22 18:22:06 +0000 |
| commit | ac92e77bb8e585065caf595c590085971b13f0f4 (patch) | |
| tree | 515338384bc933969f301022b9e878318ec2dff9 | |
| parent | fe29fe431d9463123b2b1e6543629ecb6c57beaa (diff) | |
| download | bcm5719-llvm-ac92e77bb8e585065caf595c590085971b13f0f4.tar.gz bcm5719-llvm-ac92e77bb8e585065caf595c590085971b13f0f4.zip | |
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
llvm-svn: 138251
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/neon.txt | 4 |
2 files changed, 8 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index ebcb798969c..725a8a2abd4 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1992,7 +1992,7 @@ static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, if (regs == 2) { CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); } - if (Rm == 0xD) { + if (Rm != 0xF) { CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); } @@ -2023,7 +2023,7 @@ static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); - if (Rm == 0xD) { + if (Rm != 0xF) { CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); } @@ -2052,7 +2052,7 @@ static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); - if (Rm == 0xD) { + if (Rm != 0xF) { CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); } @@ -2097,7 +2097,7 @@ static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); - if (Rm == 0xD) { + if (Rm != 0xF) { CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); } diff --git a/llvm/test/MC/Disassembler/ARM/neon.txt b/llvm/test/MC/Disassembler/ARM/neon.txt index d9482d7006c..b909c4bb4bc 100644 --- a/llvm/test/MC/Disassembler/ARM/neon.txt +++ b/llvm/test/MC/Disassembler/ARM/neon.txt @@ -1845,3 +1845,7 @@ # CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] 0x4f 0x1b 0xc0 0xf4 # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] + +0x0 0xc 0xa0 0xf4 +# CHECK: vld1.8 {d0[]}, [r0], r0 + |
