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| author | Daniel Kiss <daniel.kiss@arm.com> | 2020-02-13 10:42:39 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2020-06-16 20:05:14 -0700 |
| commit | aab50695971617d37ad420b476671995f7078e79 (patch) | |
| tree | cfe7c3fcce40d3a7f459c0604db720796235ccdd | |
| parent | b980cc1cd3200dbf7603c7dd04335165b7578baa (diff) | |
| download | bcm5719-llvm-aab50695971617d37ad420b476671995f7078e79.tar.gz bcm5719-llvm-aab50695971617d37ad420b476671995f7078e79.zip | |
[AArch64] Fix BTI landing pad generation.
In some cases BTI landing pad is inserted even compatible instruction
was there already. Meta instruction does not count in this case
therefore skip them in the check for first instructions in the function.
Differential revision: https://reviews.llvm.org/D74492
(cherry picked from commit d5a186a60014dc1a8c979c978cb32aba7ecb9102)
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64BranchTargets.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/branch-target-enforcement.mir | 31 |
2 files changed, 35 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp b/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp index 6fa3a462bc7..be6450c9a45 100644 --- a/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp +++ b/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp @@ -118,6 +118,10 @@ void AArch64BranchTargets::addBTI(MachineBasicBlock &MBB, bool CouldCall, auto MBBI = MBB.begin(); + // Skip the meta instuctions, those will be removed anyway. + for (; MBBI != MBB.end() && MBBI->isMetaInstruction(); ++MBBI) + ; + // PACI[AB]SP are implicitly BTI JC, so no BTI instruction needed there. if (MBBI != MBB.end() && (MBBI->getOpcode() == AArch64::PACIASP || MBBI->getOpcode() == AArch64::PACIBSP)) diff --git a/llvm/test/CodeGen/AArch64/branch-target-enforcement.mir b/llvm/test/CodeGen/AArch64/branch-target-enforcement.mir index e0eff1e2de8..99da912207d 100644 --- a/llvm/test/CodeGen/AArch64/branch-target-enforcement.mir +++ b/llvm/test/CodeGen/AArch64/branch-target-enforcement.mir @@ -97,6 +97,12 @@ ret i32 %merge2 } + define hidden i32 @debug_ptr_auth() "branch-target-enforcement" { + entry: + tail call void asm sideeffect "", "~{lr}"() + ret i32 0 + } + ... --- # External function, could be addres-taken elsewhere so needs BTI JC. @@ -321,5 +327,30 @@ body: | renamable $x9 = ADDXri killed $x9, target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@label_address, %ir-block.return), 0 STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (store 8 into @label_address.addr) RET undef $lr, implicit killed $w0 +--- +# When PACIASP is the first real instruction in the functions then BTI should not be inserted. +name: debug_ptr_auth +stack: + - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16, + stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.0.entry: + liveins: $lr + + ; CHECK-LABEL: name: debug_ptr_auth + ; CHECK-NOT: HINT + ; CHECK: DBG_VALUE + ; CHECK: frame-setup PACIASP + ; CHECK-NOT: HINT + ; CHECK: RETAA + DBG_VALUE $lr + frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp + frame-setup CFI_INSTRUCTION negate_ra_sign_state + early-clobber $sp = frame-setup STRXpre killed $lr, $sp, -16 :: (store 8 into %stack.0) + INLINEASM &"", 1, 12, implicit-def dead early-clobber $lr + $w0 = ORRWrs $wzr, $wzr, 0 + early-clobber $sp, $lr = frame-destroy LDRXpost $sp, 16 :: (load 8 from %stack.0) + RETAA implicit $sp, implicit $lr, implicit killed $w0 ... |
