diff options
author | Evan Cheng <evan.cheng@apple.com> | 2011-10-17 19:50:12 +0000 |
---|---|---|
committer | Evan Cheng <evan.cheng@apple.com> | 2011-10-17 19:50:12 +0000 |
commit | aa563df75974aa714270d48fa1b668baf893be0b (patch) | |
tree | 10520b965c8f249e24ddcf8fd41c185a73e6d066 | |
parent | dc199a3152b15936b13f47befe4d18bf74c75c33 (diff) | |
download | bcm5719-llvm-aa563df75974aa714270d48fa1b668baf893be0b.tar.gz bcm5719-llvm-aa563df75974aa714270d48fa1b668baf893be0b.zip |
Constraint register class with constrainRegClass() to CSE a virtual into another. rdar://10293289
llvm-svn: 142234
-rw-r--r-- | llvm/lib/CodeGen/MachineLICM.cpp | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp index 8f7a8ebb264..969a9b084d5 100644 --- a/llvm/lib/CodeGen/MachineLICM.cpp +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -1196,6 +1196,7 @@ bool MachineLICM::EliminateCSE(MachineInstr *MI, // Replace virtual registers defined by MI by their counterparts defined // by Dup. + SmallVector<unsigned, 2> Defs; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); @@ -1206,11 +1207,33 @@ bool MachineLICM::EliminateCSE(MachineInstr *MI, "Instructions with different phys regs are not identical!"); if (MO.isReg() && MO.isDef() && - !TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { - MRI->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg()); - MRI->clearKillFlags(Dup->getOperand(i).getReg()); + !TargetRegisterInfo::isPhysicalRegister(MO.getReg())) + Defs.push_back(i); + } + + SmallVector<const TargetRegisterClass*, 2> OrigRCs; + for (unsigned i = 0, e = Defs.size(); i != e; ++i) { + unsigned Idx = Defs[i]; + unsigned Reg = MI->getOperand(Idx).getReg(); + unsigned DupReg = Dup->getOperand(Idx).getReg(); + OrigRCs.push_back(MRI->getRegClass(DupReg)); + + if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) { + // Restore old RCs if more than one defs. + for (unsigned j = 0; j != i; ++j) + MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]); + return false; } } + + for (unsigned i = 0, e = Defs.size(); i != e; ++i) { + unsigned Idx = Defs[i]; + unsigned Reg = MI->getOperand(Idx).getReg(); + unsigned DupReg = Dup->getOperand(Idx).getReg(); + MRI->replaceRegWith(Reg, DupReg); + MRI->clearKillFlags(DupReg); + } + MI->eraseFromParent(); ++NumCSEed; return true; |