initial implementation of ARMRegisterInfo::eliminateFrameIndex

fixes test/Regression/CodeGen/ARM/ret_arg5.ll

llvm-svn: 28854

4 files changed, 34 insertions, 3 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index c508754f194..6ac9b0482ad 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -53,3 +53,7 @@ def movrr   : InstARM<(ops IntRegs:$dst, IntRegs:$src),
 
 def movri   : InstARM<(ops IntRegs:$dst, i32imm:$src),
                        "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
+
+def addri   : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
+                       "add $dst, $a, $b",
+		       [(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index 18e273134c5..e4ae851dd83 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -77,7 +77,29 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 
 void
 ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
-  assert(0 && "Not Implemented");
+  MachineInstr &MI = *II;
+  MachineBasicBlock &MBB = *MI.getParent();
+  MachineFunction &MF = *MBB.getParent();
+
+  assert (MI.getOpcode() == ARM::movrr);
+
+  unsigned FrameIdx = 1;
+
+  int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
+
+  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
+
+  unsigned StackSize = MF.getFrameInfo()->getStackSize();
+
+  Offset += StackSize;
+
+  // Insert a set of r12 with the full address
+  // r12 = r13 + offset
+  MachineBasicBlock *MBB2 = MI.getParent();
+  BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
+
+  // Replace the FrameIndex with r12
+  MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
 }
 
 void ARMRegisterInfo::
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td
index e53ab8bfe7e..5d61cc432fc 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.td
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td
@@ -50,7 +50,13 @@ def IntRegs : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
   let MethodBodies = [{
     IntRegsClass::iterator
     IntRegsClass::allocation_order_end(MachineFunction &MF) const {
-      return end() - 1;
+      // r15 == Program Counter
+      // r14 == Link Register
+      // r13 == Stack Pointer
+      // r12 == ip (scratch)
+      // r11 == Frame Pointer
+      // r10 == Stack Limit
+      return end() - 4;
     }
   }];
 }
diff --git a/llvm/test/Regression/CodeGen/ARM/ret_arg5.ll b/llvm/test/Regression/CodeGen/ARM/ret_arg5.ll
index a42ee951501..e434bcab284 100644
--- a/llvm/test/Regression/CodeGen/ARM/ret_arg5.ll
+++ b/llvm/test/Regression/CodeGen/ARM/ret_arg5.ll
@@ -1,5 +1,4 @@
 ; RUN: llvm-as < %s | llc -march=arm
-; XFAIL: *
 int %test(int %a1, int %a2, int %a3, int %a4, int %a5) {
   ret int %a5
 }