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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-21 15:17:23 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-21 15:17:23 +0000 |
| commit | a8869e68a9ace4f1c6fe8075d47172803516f170 (patch) | |
| tree | 395bac6439e26c0da80ea480843d05faa4b67144 | |
| parent | fe76b36ab1286a1248e7a302dcca4245e91714ad (diff) | |
| download | bcm5719-llvm-a8869e68a9ace4f1c6fe8075d47172803516f170.tar.gz bcm5719-llvm-a8869e68a9ace4f1c6fe8075d47172803516f170.zip | |
[X86][SSE] Add an assert to ensure that rotation amount is converted to a scale
Missed in rL332832 where we added SSE v4i32 rotations for PR37426.
llvm-svn: 332844
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 8809c9c613a..4614e24beca 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23825,6 +23825,7 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget, // to v2i64 results at a time. The upper 32-bits contain the wrapped bits // that can then be OR'd with the lower 32-bits. Amt = convertShiftLeftToScale(Amt, DL, Subtarget, DAG); + assert(Amt && "Failed to convert ROTL amount to scale"); static const int OddMask[] = {1, -1, 3, -1}; SDValue R13 = DAG.getVectorShuffle(VT, DL, R, R, OddMask); |
