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authorChad Rosier <mcrosier@apple.com>2012-11-30 18:29:01 +0000
committerChad Rosier <mcrosier@apple.com>2012-11-30 18:29:01 +0000
commita820e7feffdb4ed21eead966fc283d5737d43846 (patch)
tree02fb209331290234cbce48772c0658e789a994e2
parentd05418eac64fab995518fbbf93d566267f1db87e (diff)
downloadbcm5719-llvm-a820e7feffdb4ed21eead966fc283d5737d43846.tar.gz
bcm5719-llvm-a820e7feffdb4ed21eead966fc283d5737d43846.zip
test/CodeGen/PowerPC/vec_mul.ll: Fix register operands.
llvm-svn: 169020
-rw-r--r--llvm/test/CodeGen/PowerPC/vec_mul.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vec_mul.ll b/llvm/test/CodeGen/PowerPC/vec_mul.ll
index df83bf1d1d1..dadf0ebb776 100644
--- a/llvm/test/CodeGen/PowerPC/vec_mul.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_mul.ll
@@ -41,6 +41,6 @@ define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
; all bits set and shifting it 31 bits to left, resulting a an vector of
; 4 x 0x80000000 (-0.0 as float).
; CHECK: test_float:
-; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
-; CHECK: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
+; CHECK: vspltisw [[ZNEG:v[0-9]+]], -1
+; CHECK: vslw {{v[0-9]+}}, [[ZNEG]], [[ZNEG]]
; CHECK: vmaddfp
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