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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-08-02 01:10:28 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-08-02 01:10:28 +0000 |
| commit | a80c8770f9506277cd4768fdddda0b78444b6ab2 (patch) | |
| tree | 382731326b08a5b30342474b45c279a1dd065624 | |
| parent | 228dda5ac5135ed4999326e127ddd6fa9b3b386b (diff) | |
| download | bcm5719-llvm-a80c8770f9506277cd4768fdddda0b78444b6ab2.tar.gz bcm5719-llvm-a80c8770f9506277cd4768fdddda0b78444b6ab2.zip | |
R600/SI: Fix formatting.
Avoid weird line wrapping of BuildMI dest register.
llvm-svn: 214608
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 50 |
1 files changed, 28 insertions, 22 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index 36afe5792a3..f031e6e53a4 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -587,14 +587,16 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo()); + + DebugLoc DL = MI->getDebugLoc(); + unsigned DestReg = MI->getOperand(0).getReg(); unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), - Reg) - .addImm(0x7fffffff); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32), - MI->getOperand(0).getReg()) - .addReg(MI->getOperand(1).getReg()) - .addReg(Reg); + + BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg) + .addImm(0x7fffffff); + BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), DestReg) + .addReg(MI->getOperand(1).getReg()) + .addReg(Reg); MI->eraseFromParent(); break; } @@ -602,28 +604,32 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo()); + + DebugLoc DL = MI->getDebugLoc(); + unsigned DestReg = MI->getOperand(0).getReg(); unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), - Reg) - .addImm(0x80000000); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32), - MI->getOperand(0).getReg()) - .addReg(MI->getOperand(1).getReg()) - .addReg(Reg); + + BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg) + .addImm(0x80000000); + BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), DestReg) + .addReg(MI->getOperand(1).getReg()) + .addReg(Reg); MI->eraseFromParent(); break; } case AMDGPU::FCLAMP_SI: { const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo()); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64), - MI->getOperand(0).getReg()) - .addImm(0) // SRC0 modifiers - .addOperand(MI->getOperand(1)) - .addImm(0) // SRC1 modifiers - .addImm(0) // SRC1 - .addImm(1) // CLAMP - .addImm(0); // OMOD + + DebugLoc DL = MI->getDebugLoc(); + unsigned DestReg = MI->getOperand(0).getReg(); + BuildMI(*BB, I, DL, TII->get(AMDGPU::V_ADD_F32_e64), DestReg) + .addImm(0) // SRC0 modifiers + .addOperand(MI->getOperand(1)) + .addImm(0) // SRC1 modifiers + .addImm(0) // SRC1 + .addImm(1) // CLAMP + .addImm(0); // OMOD MI->eraseFromParent(); } } |
