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author | Hal Finkel <hfinkel@anl.gov> | 2014-02-02 06:12:27 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2014-02-02 06:12:27 +0000 |
commit | a7bbaf6de6e5c24fe1a19959d39583bb412fd764 (patch) | |
tree | e4dee241718a90856c2a32ae0d44447cdd33e490 | |
parent | 3e3305dabaa26116be315cc758fc4d9ec3a7aba1 (diff) | |
download | bcm5719-llvm-a7bbaf6de6e5c24fe1a19959d39583bb412fd764.tar.gz bcm5719-llvm-a7bbaf6de6e5c24fe1a19959d39583bb412fd764.zip |
Replace PPC instruction-size code with MCInstrDesc getSize
As part of the cleanup done to enable the disassembler, the PPC instructions
now have a valid Size description field. This can now be used to replace some
custom logic in a few places to compute instruction sizes.
Patch by David Wiberg!
llvm-svn: 200623
-rw-r--r-- | llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 12 | ||||
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 19 |
2 files changed, 11 insertions, 20 deletions
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index f1b2802c9ec..93e6fc76322 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -33,10 +33,12 @@ class PPCMCCodeEmitter : public MCCodeEmitter { PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION; void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION; + const MCInstrInfo &MCII; const MCContext &CTX; public: - PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) : CTX(ctx) { + PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) + : MCII(mcii), CTX(ctx) { } ~PPCMCCodeEmitter() {} @@ -90,18 +92,14 @@ public: // It's just a nop to keep the register classes happy, so don't // generate anything. unsigned Opcode = MI.getOpcode(); + const MCInstrDesc &Desc = MCII.get(Opcode); if (Opcode == TargetOpcode::COPY_TO_REGCLASS) return; uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); - // BL8_NOP etc. all have a size of 8 because of the following 'nop'. - unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value! - if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP || - Opcode == PPC::BL8_NOP_TLS) - Size = 8; - // Output the constant in big endian byte order. + unsigned Size = Desc.getSize(); int ShiftValue = (Size * 8) - 8; for (unsigned i = 0; i != Size; ++i) { OS << (char)(Bits >> ShiftValue); diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 9e491fa19c2..b15ef1b9a6d 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1436,22 +1436,15 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr, /// instruction may be. This returns the maximum number of bytes. /// unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { - switch (MI->getOpcode()) { - case PPC::INLINEASM: { // Inline Asm: Variable size. + unsigned Opcode = MI->getOpcode(); + + if (Opcode == PPC::INLINEASM) { const MachineFunction *MF = MI->getParent()->getParent(); const char *AsmStr = MI->getOperand(0).getSymbolName(); return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); - } - case PPC::PROLOG_LABEL: - case PPC::EH_LABEL: - case PPC::GC_LABEL: - case PPC::DBG_VALUE: - return 0; - case PPC::BL8_NOP: - case PPC::BLA8_NOP: - return 8; - default: - return 4; // PowerPC instructions are all 4 bytes + } else { + const MCInstrDesc &Desc = get(Opcode); + return Desc.getSize(); } } |