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| author | Dan Gohman <gohman@apple.com> | 2008-08-13 19:47:40 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-08-13 19:47:40 +0000 |
| commit | a7b8aed469a2567f03b40ab848b880bf116c92c6 (patch) | |
| tree | 4bbc17007d5fc682c01bcb59a60aa7b13aa89598 | |
| parent | a7a2f22fe52c2950e83a59f29f535276cd80d18b (diff) | |
| download | bcm5719-llvm-a7b8aed469a2567f03b40ab848b880bf116c92c6.tar.gz bcm5719-llvm-a7b8aed469a2567f03b40ab848b880bf116c92c6.zip | |
Rename SelectionDAGISel's FastISel to Fast, to begin to make
room for the new FastISel instruction selection code.
llvm-svn: 54749
| -rw-r--r-- | llvm/include/llvm/CodeGen/SelectionDAGISel.h | 4 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h index 804ccf3e590..74710394770 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -42,12 +42,12 @@ public: MachineBasicBlock *BB; AliasAnalysis *AA; CollectorMetadata *GCI; - bool FastISel; + bool Fast; std::vector<SDNode*> TopOrder; static char ID; explicit SelectionDAGISel(TargetLowering &tli, bool fast = false) : - FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), FastISel(fast), DAGSize(0) {} + FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), Fast(fast), DAGSize(0) {} TargetLowering &getTargetLowering() { return TLI; } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index d1c49d00eed..815fdb7cc74 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -5379,7 +5379,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName); - if (!FastISel && EnableValueProp) + if (!Fast && EnableValueProp) ComputeLiveOutVRegInfo(DAG); // Third, instruction select all of the operations to machine code, adding the @@ -5448,7 +5448,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF, BasicBlock *LLVMBB = &*I; PHINodesToUpdate.clear(); - if (!FastISel || !SISel.SelectBasicBlock(LLVMBB, FuncInfo.MBBMap[LLVMBB])) + if (!Fast || !SISel.SelectBasicBlock(LLVMBB, FuncInfo.MBBMap[LLVMBB])) SelectBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator); FinishBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator); } @@ -5696,7 +5696,7 @@ ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) { RegisterScheduler::setDefault(Ctor); } - ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel); + ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, Fast); Scheduler->Run(); return Scheduler; |
