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authorCraig Topper <craig.topper@gmail.com>2016-05-26 04:28:45 +0000
committerCraig Topper <craig.topper@gmail.com>2016-05-26 04:28:45 +0000
commita423aa4642f4272a108ce0a6c8f833afc18a6438 (patch)
tree419d27484e18aa0c5a5290002bd90097324dab23
parent0bc8994a4cf1e2a2c69629a613263b741b87f2fc (diff)
downloadbcm5719-llvm-a423aa4642f4272a108ce0a6c8f833afc18a6438.tar.gz
bcm5719-llvm-a423aa4642f4272a108ce0a6c8f833afc18a6438.zip
[X86] Add the AVX storeu intrinsics to InstCombine and LoopStrengthReduce in the same places that the SSE/SSE2 storeu intrinsics appear.
I don't really know how to test this. Just seemed like we should be consistent. llvm-svn: 270819
-rw-r--r--llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp13
-rw-r--r--llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp6
2 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
index d49b7b8ea9d..c07ca85d3a4 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -1428,6 +1428,19 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
}
break;
+ case Intrinsic::x86_avx_storeu_ps_256:
+ case Intrinsic::x86_avx_storeu_pd_256:
+ case Intrinsic::x86_avx_storeu_dq_256:
+ // Turn X86 storeu -> store if the pointer is known aligned.
+ if (getOrEnforceKnownAlignment(II->getArgOperand(0), 32, DL, II, AC, DT) >=
+ 32) {
+ Type *OpPtrTy =
+ PointerType::getUnqual(II->getArgOperand(1)->getType());
+ Value *Ptr = Builder->CreateBitCast(II->getArgOperand(0), OpPtrTy);
+ return new StoreInst(II->getArgOperand(1), Ptr);
+ }
+ break;
+
case Intrinsic::x86_vcvtph2ps_128:
case Intrinsic::x86_vcvtph2ps_256: {
auto Arg = II->getArgOperand(0);
diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index b5afe0a62ce..ad70a70a0d6 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -687,6 +687,9 @@ static bool isAddressUse(Instruction *Inst, Value *OperandVal) {
case Intrinsic::x86_sse_storeu_ps:
case Intrinsic::x86_sse2_storeu_pd:
case Intrinsic::x86_sse2_storeu_dq:
+ case Intrinsic::x86_avx_storeu_ps_256:
+ case Intrinsic::x86_avx_storeu_pd_256:
+ case Intrinsic::x86_avx_storeu_dq_256:
if (II->getArgOperand(0) == OperandVal)
isAddress = true;
break;
@@ -711,6 +714,9 @@ static MemAccessTy getAccessType(const Instruction *Inst) {
case Intrinsic::x86_sse_storeu_ps:
case Intrinsic::x86_sse2_storeu_pd:
case Intrinsic::x86_sse2_storeu_dq:
+ case Intrinsic::x86_avx_storeu_ps_256:
+ case Intrinsic::x86_avx_storeu_pd_256:
+ case Intrinsic::x86_avx_storeu_dq_256:
AccessTy.MemTy = II->getArgOperand(0)->getType();
break;
}
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