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| author | Jim Grosbach <grosbach@apple.com> | 2010-09-14 21:28:17 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-09-14 21:28:17 +0000 |
| commit | a244f70113dee9627c78cacc4dca820d8bc8123a (patch) | |
| tree | e2ea6460ca41bba51a5b41ea4ff8ea968d02f076 | |
| parent | 36e54c99433c7776bb3586358c63c93774d22589 (diff) | |
| download | bcm5719-llvm-a244f70113dee9627c78cacc4dca820d8bc8123a.tar.gz bcm5719-llvm-a244f70113dee9627c78cacc4dca820d8bc8123a.zip | |
Add predicate and 's' bit operands to PICADD instruction lowering.
llvm-svn: 113860
| -rw-r--r-- | llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index 47d68fa80d2..067d1a6bf89 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -1349,6 +1349,11 @@ void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) { AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); AddInst.addOperand(MCOperand::CreateReg(ARM::PC)); AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); + // Add predicate operands. + AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); + AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg())); + // Add 's' bit operand (always reg0 for this) + AddInst.addOperand(MCOperand::CreateReg(0)); OutStreamer.EmitInstruction(AddInst); return; } |
