[X86] Add the 16 and 8-bit CRC32 instructions to the load folding tables.

llvm-svn: 321958

3 files changed, 19 insertions, 9 deletions

diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 92b3f311db9..88b608d3e45 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -1217,8 +1217,11 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
     { X86::CMPSDrr_Int,     X86::CMPSDrm_Int,   TB_NO_REVERSE },
     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
     { X86::CMPSSrr_Int,     X86::CMPSSrm_Int,   TB_NO_REVERSE },
+    { X86::CRC32r32r16,     X86::CRC32r32m16,   0 },
     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
+    { X86::CRC32r32r8,      X86::CRC32r32m8,    0 },
     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
+    { X86::CRC32r64r8,      X86::CRC32r64m8,    0 },
     { X86::CVTSD2SSrr_Int,  X86::CVTSD2SSrm_Int,      TB_NO_REVERSE },
     { X86::CVTSS2SDrr_Int,  X86::CVTSS2SDrm_Int,      TB_NO_REVERSE },
     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
diff --git a/llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll
index f8d7f61d206..8ff3fae6509 100644
--- a/llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll
@@ -354,9 +354,8 @@ declare i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8>, <16 x i8>, i8) nounwind rea
 define i32 @test_mm_crc32_u8(i32 %a0, i8 %a1) {
 ; X32-LABEL: test_mm_crc32_u8:
 ; X32:       # %bb.0:
-; X32-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    crc32b %cl, %eax
+; X32-NEXT:    crc32b {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_crc32_u8:
@@ -372,9 +371,8 @@ declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind readnone
 define i32 @test_mm_crc32_u16(i32 %a0, i16 %a1) {
 ; X32-LABEL: test_mm_crc32_u16:
 ; X32:       # %bb.0:
-; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    crc32w %cx, %eax
+; X32-NEXT:    crc32w {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_crc32_u16:
diff --git a/llvm/test/CodeGen/X86/stack-folding-int-sse42.ll b/llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
index 136077e2917..7f307681178 100644
--- a/llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
+++ b/llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
@@ -62,10 +62,22 @@ define <2 x i64> @stack_fold_aeskeygenassist(<2 x i64> %a0) {
 }
 declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8) nounwind readnone
 
-;TODO stack_fold_crc32_32_8
+define i32 @stack_fold_crc32_32_8(i32 %a0, i8 %a1) {
+  ;CHECK-LABEL: stack_fold_crc32_32_8
+  ;CHECK:       crc32b {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 1-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a0, i8 %a1)
+  ret i32 %2
+}
 declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
 
-;TODO stack_fold_crc32_32_16
+define i32 @stack_fold_crc32_32_16(i32 %a0, i16 %a1) {
+  ;CHECK-LABEL: stack_fold_crc32_32_16
+  ;CHECK:       crc32w {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 2-byte Folded Reload
+  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a0, i16 %a1)
+  ret i32 %2
+}
 declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
 
 define i32 @stack_fold_crc32_32_32(i32 %a0, i32 %a1) {
@@ -77,9 +89,6 @@ define i32 @stack_fold_crc32_32_32(i32 %a0, i32 %a1) {
 }
 declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind
 
-;TODO stack_fold_crc32_64_8
-declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind
-
 define i64 @stack_fold_crc32_64_64(i64 %a0, i64 %a1) {
   ;CHECK-LABEL: stack_fold_crc32_64_64
   ;CHECK:       crc32q {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload