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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-07-01 20:28:30 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-07-01 20:28:30 +0000
commita17250d8e042f6fe1ddd4beaffcfafa3806aee86 (patch)
treed3afce89cada1f9657dc60873a3cc302877e79ad
parent7f8827576cf6ab35e0e19aeeaede34289737115e (diff)
downloadbcm5719-llvm-a17250d8e042f6fe1ddd4beaffcfafa3806aee86.tar.gz
bcm5719-llvm-a17250d8e042f6fe1ddd4beaffcfafa3806aee86.zip
[Hexagon] Use MachineOperand::readsReg instead of isUse
llvm-svn: 274381
-rw-r--r--llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 6f65e2203a6..05329211f52 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -349,7 +349,7 @@ void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
// Set the <kill> flag on a use of Reg whose lane mask is contained in LM.
MachineInstr *MI = LIS->getInstructionFromIndex(K);
for (auto &Op : MI->operands()) {
- if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
+ if (!Op.isReg() || !Op.readsReg() || Op.getReg() != Reg)
continue;
LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
if ((SLM & LM) == SLM) {
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