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| author | Sam Parker <sam.parker@arm.com> | 2019-06-03 08:49:17 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2019-06-03 08:49:17 +0000 |
| commit | a0bd6f8a1ae73887fc32b85cd44e85435310f9d3 (patch) | |
| tree | 3ee77677b483713a47d63167ec60173a3d1e8ce6 | |
| parent | bcd542881ddcfc6647d7c0892f7c8a6f4fdc5f49 (diff) | |
| download | bcm5719-llvm-a0bd6f8a1ae73887fc32b85cd44e85435310f9d3.tar.gz bcm5719-llvm-a0bd6f8a1ae73887fc32b85cd44e85435310f9d3.zip | |
[AArch64] Check for simple type in FPToUInt
DAGCombiner was hitting a SimpleType assertion when trying to combine
a v3f32 before type legalization.
bugzilla: https://bugs.llvm.org/show_bug.cgi?id=41916
Differential Revision: https://reviews.llvm.org/D62734
llvm-svn: 362365
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/v3f-to-int.ll | 17 |
2 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index d8e52929ffb..ba8bbd25159 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -9206,6 +9206,9 @@ static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG, if (!Subtarget->hasNEON()) return SDValue(); + if (!N->getValueType(0).isSimple()) + return SDValue(); + SDValue Op = N->getOperand(0); if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() || Op.getOpcode() != ISD::FMUL) diff --git a/llvm/test/CodeGen/AArch64/v3f-to-int.ll b/llvm/test/CodeGen/AArch64/v3f-to-int.ll new file mode 100644 index 00000000000..9c9dd5ed7e9 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/v3f-to-int.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=aarch64--linux-eabi %s -o - | FileCheck %s + +; CHECK-LABEL: convert_v3f32 +; CHECK: strb +; CHECK: strh +define void @convert_v3f32() { +entry: + br label %bb + +bb: + %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> + %1 = fmul reassoc nnan ninf nsz contract afn <3 x float> %0, <float 2.550000e+02, float 2.550000e+02, float 2.550000e+02> + %2 = fptoui <3 x float> %1 to <3 x i8> + %3 = bitcast i8* undef to <3 x i8>* + store <3 x i8> %2, <3 x i8>* %3, align 1 + ret void +} |
