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| author | Quentin Colombet <qcolombet@apple.com> | 2016-05-06 21:21:50 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2016-05-06 21:21:50 +0000 |
| commit | a09f050dc1ab607b11daa5f1c32210b1ed9f04bd (patch) | |
| tree | 79853b2ec9f0a44d3f45cce1ef5209790d1b7e31 | |
| parent | 4f84e3bfcfe1fff40192b2e95262fcff1db7a8af (diff) | |
| download | bcm5719-llvm-a09f050dc1ab607b11daa5f1c32210b1ed9f04bd.tar.gz bcm5719-llvm-a09f050dc1ab607b11daa5f1c32210b1ed9f04bd.zip | |
Revert "[X86] Add a new LOW32_ADDR_ACCESS_RBP register class."
This reverts commit r268796.
I believe it breaks test/CodeGen/X86/asm-mismatched-types.ll with:
Cannot emit physreg copy instruction
llvm-svn: 268799
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.td | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll | 6 |
3 files changed, 4 insertions, 17 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index cb4170cc623..e32a5fdcdba 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -166,15 +166,7 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, // we can still use 64-bit register as long as we know the high bits // are zeros. // Reflect that in the returned register class. - if (Is64Bit) { - // When the target also allows 64-bit frame pointer and we do have a - // frame, this is fine to use it for the address accesses as well. - const X86FrameLowering *TFI = getFrameLowering(MF); - return TFI->hasFP(MF) && TFI->Uses64BitFramePtr - ? &X86::LOW32_ADDR_ACCESS_RBPRegClass - : &X86::LOW32_ADDR_ACCESSRegClass; - } - return &X86::GR32RegClass; + return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass; case 1: // Normal GPRs except the stack pointer (for encoding reasons). if (Subtarget.isTarget64BitLP64()) return &X86::GR64_NOSPRegClass; diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index d3544beae61..3c50ac7ce50 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -427,11 +427,6 @@ def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, // which we do not have right now. def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>; -// When RBP is used as a base pointer in a 32-bit addresses environement, -// this is also safe to use the full register to access addresses. -def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 64, - (add LOW32_ADDR_ACCESS, RBP)>; - // A class to support the 'A' assembler constraint: EAX then EDX. def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; diff --git a/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll b/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll index b1f4ca56223..c476ffd8405 100644 --- a/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll +++ b/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s -; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s +; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s +; RUN: llc -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s ; x32 uses %esp, %ebp as stack and frame pointers |
