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| author | Evan Cheng <evan.cheng@apple.com> | 2007-08-09 18:05:17 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-08-09 18:05:17 +0000 |
| commit | a05ec4dc525e84292ff6e6ee27e941dd0c67b976 (patch) | |
| tree | fef6b45182c9e03aa9151828e7d9ebe0b4585802 | |
| parent | 8f184b12fcee4913c2da61a2fbc86561b56ec02c (diff) | |
| download | bcm5719-llvm-a05ec4dc525e84292ff6e6ee27e941dd0c67b976.tar.gz bcm5719-llvm-a05ec4dc525e84292ff6e6ee27e941dd0c67b976.zip | |
GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_.
llvm-svn: 40970
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.td | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index dba96669ae8..a5b218999c4 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -417,13 +417,14 @@ def GR64 : RegisterClass<"X86", [i64], 64, } -// GR16, GR32 subclasses which contain registers that have R8 sub-registers. +// GR16, GR32 subclasses which contain registers that have GR8 sub-registers. // These should only be used for 32-bit mode. +def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL, AH, CH, DH, BH]>; def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> { - let SubRegClassList = [GR8]; + let SubRegClassList = [GR8_]; } def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> { - let SubRegClassList = [GR8, GR16]; + let SubRegClassList = [GR8_, GR16_]; } // Scalar SSE2 floating point registers. |
