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authorCraig Topper <craig.topper@intel.com>2018-12-13 06:14:25 +0000
committerCraig Topper <craig.topper@intel.com>2018-12-13 06:14:25 +0000
commita048d58de72d830a04e4dcbdc1f7beed87884479 (patch)
tree78d6f5466ac2600e5756b998e1878f501f29f5ad
parentd933c2ced7f9518188c7b3281f71da899c1447bd (diff)
downloadbcm5719-llvm-a048d58de72d830a04e4dcbdc1f7beed87884479.tar.gz
bcm5719-llvm-a048d58de72d830a04e4dcbdc1f7beed87884479.zip
[X86] Remove assert leftover from when i1 was a legal type. Add more accurate assert. NFC
llvm-svn: 349007
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp4
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d61bfe54651..070dabd4e52 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18815,9 +18815,6 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
if (isNullConstant(Op1))
return EmitTest(Op0, X86CC, dl, DAG);
- assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
- "Unexpected comparison operation for MVT::i1 operands");
-
if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
// Only promote the compare up to I32 if it is a 16 bit operation
@@ -18839,6 +18836,7 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, Op0, Op1);
return SDValue(Sub.getNode(), 1);
}
+ assert(Op0.getValueType().isFloatingPoint() && "Unexpected VT!");
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
}
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