Revert "[AMDGPU] Fix for SIMachineScheduler crash. SI Scheduler should track"

This reverts commit ce06d9cb99298eb844b66e117f5108a06747c907.

llvm-svn: 295054

3 files changed, 4 insertions, 52 deletions

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
index c377a0af350..ec5ba2e9d14 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -262,7 +262,9 @@ void SISubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
   Policy.OnlyTopDown = false;
   Policy.OnlyBottomUp = false;
 
-  Policy.ShouldTrackLaneMasks = enableSubRegLiveness();
+  // Enabling ShouldTrackLaneMasks crashes the SI Machine Scheduler.
+  if (!enableSIScheduler())
+    Policy.ShouldTrackLaneMasks = true;
 }
 
 bool SISubtarget::isVGPRSpillingEnabled(const Function& F) const {
diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.h b/llvm/lib/Target/AMDGPU/SIMachineScheduler.h
index 02cfa509d3d..2dc4b346de7 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.h
@@ -440,8 +440,7 @@ public:
 
   // To init Block's RPTracker.
   void initRPTracker(RegPressureTracker &RPTracker) {
-    RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin,
-     MF.getSubtarget().enableSubRegLiveness(), false);
+    RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false);
   }
 
   MachineBasicBlock *getBB() { return BB; }
diff --git a/llvm/test/CodeGen/AMDGPU/si-shed-track-subregs.ll b/llvm/test/CodeGen/AMDGPU/si-shed-track-subregs.ll
deleted file mode 100644
index 0b65a0b33e2..00000000000
--- a/llvm/test/CodeGen/AMDGPU/si-shed-track-subregs.ll
+++ /dev/null
@@ -1,49 +0,0 @@
-; This test does not check anything. Just ensure no crash.
-; RUN: llc -O2 -mtriple amdgcn--amdhsa --misched=si -mattr=si-scheduler -mcpu=fiji -filetype=asm < %s
-
-declare i32 @llvm.amdgcn.workitem.id.x() #4
-
-declare i32 @llvm.amdgcn.workitem.id.y() #4
-
-define amdgpu_kernel void @"test"(float addrspace(1)* nocapture,
- [4 x [4 x float]] addrspace(3) *,
- [4 x [4 x float]] addrspace(3) *,
- [4 x [4 x float]] addrspace(3) *,
- [4 x [4 x float]] addrspace(3) *
-) {
-
-  %st_addr = getelementptr float, float addrspace(1)* %0, i64 10
-  %id_x = tail call i32 @llvm.amdgcn.workitem.id.x() #4
-  %id_y = tail call i32 @llvm.amdgcn.workitem.id.y() #4
-
-  %6  = getelementptr [4 x [4 x float]], [4 x [4 x float]] addrspace(3)* %1, i32 0, i32 %id_y, i32 1234
-  %7  = getelementptr [4 x [4 x float]], [4 x [4 x float]] addrspace(3)* %2, i32 0, i32 0, i32 %id_x
-  %8  = getelementptr [4 x [4 x float]], [4 x [4 x float]] addrspace(3)* %3, i32 0, i32 %id_y, i32 0
-  %9  = getelementptr [4 x [4 x float]], [4 x [4 x float]] addrspace(3)* %4, i32 0, i32 0, i32 %id_x
-  %10 = getelementptr [4 x [4 x float]], [4 x [4 x float]] addrspace(3)* %1, i32 0, i32 %id_y, i32 1294
-  %11 = getelementptr [4 x [4 x float]], [4 x [4 x float]] addrspace(3)* %2, i32 0, i32 1, i32 %id_x
-  %12 = getelementptr [4 x [4 x float]], [4 x [4 x float]] addrspace(3)* %3, i32 0, i32 %id_y, i32 1
-  %13 = getelementptr [4 x [4 x float]], [4 x [4 x float]] addrspace(3)* %4, i32 0, i32 1, i32 %id_x
-
-
-  %14 = load float, float addrspace(3)* %6
-  %15 = load float, float addrspace(3)* %7
-  %mul3 = fmul float %14, %15
-  %add1 = fadd float 2.0, %mul3
-  %16 = load float, float addrspace(3)* %8
-  %17 = load float, float addrspace(3)* %9
-  %mul4 = fmul float %16, %17
-  %sub2 = fsub float %add1, %mul4
-  %18 = load float, float addrspace(3)* %10
-  %19 = load float, float addrspace(3)* %11
-  %mul5 = fmul float %18, %19
-  %sub3 = fsub float %sub2, %mul5
-  %20 = load float, float addrspace(3)* %12
-  %21 = load float, float addrspace(3)* %13
-  %mul6 = fmul float %20, %21
-  %sub4 = fsub float %sub3, %mul6
-  store float %sub4, float addrspace(1)* %st_addr
-  ret void
-}
-
-attributes #4 = { nounwind readnone }