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author | Chris Lattner <sabre@nondot.org> | 2008-06-30 02:43:01 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2008-06-30 02:43:01 +0000 |
commit | 9d3740ed1cfa614125b4b8f7399787f879a18608 (patch) | |
tree | d6cb9a1c8ffa226192503ed199d7fc5d4503f5b1 | |
parent | 21d0a8cca0fffb39a66ad9c5f4258a854949414f (diff) | |
download | bcm5719-llvm-9d3740ed1cfa614125b4b8f7399787f879a18608.tar.gz bcm5719-llvm-9d3740ed1cfa614125b4b8f7399787f879a18608.zip |
Implement split and scalarize for SELECT_CC, fixing PR2504
llvm-svn: 52887
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 23 | ||||
-rw-r--r-- | llvm/test/CodeGen/Generic/select-cc.ll | 9 |
2 files changed, 32 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index f087496996a..c40a783da07 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -6895,6 +6895,22 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, } break; } + case ISD::SELECT_CC: { + SDOperand CondLHS = Node->getOperand(0); + SDOperand CondRHS = Node->getOperand(1); + SDOperand CondCode = Node->getOperand(4); + + SDOperand LL, LH, RL, RH; + SplitVectorOp(Node->getOperand(2), LL, LH); + SplitVectorOp(Node->getOperand(3), RL, RH); + + // Handle a simple select with vector operands. + Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS, + LL, RL, CondCode); + Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, + LH, RH, CondCode); + break; + } case ISD::VSETCC: { SDOperand LL, LH, RL, RH; SplitVectorOp(Node->getOperand(0), LL, LH); @@ -7122,6 +7138,13 @@ SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { ScalarizeVectorOp(Op.getOperand(1)), ScalarizeVectorOp(Op.getOperand(2))); break; + case ISD::SELECT_CC: + Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), + Node->getOperand(1), + ScalarizeVectorOp(Op.getOperand(2)), + ScalarizeVectorOp(Op.getOperand(3)), + Node->getOperand(4)); + break; case ISD::VSETCC: { SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0)); SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1)); diff --git a/llvm/test/CodeGen/Generic/select-cc.ll b/llvm/test/CodeGen/Generic/select-cc.ll new file mode 100644 index 00000000000..85e68d19c45 --- /dev/null +++ b/llvm/test/CodeGen/Generic/select-cc.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc +; PR2504 + +define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind { + %x.lo = extractelement <2 x double> %x, i32 0 ; <double> [#uses=1] + %x.lo.ge = fcmp oge double %x.lo, 0.000000e+00 ; <i1> [#uses=1] + %a.d = select i1 %x.lo.ge, <2 x double> %y, <2 x double> %x ; <<2 x double>> [#uses=1] + ret <2 x double> %a.d +} |