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| author | Guozhi Wei <carrot@google.com> | 2018-03-15 17:49:12 +0000 |
|---|---|---|
| committer | Guozhi Wei <carrot@google.com> | 2018-03-15 17:49:12 +0000 |
| commit | 9c916584ba198dfcd21cea645ac1406e399e5b30 (patch) | |
| tree | a4aab49e328976fe0786aa5ff4b13fbe6f5fb77e | |
| parent | 48b758e8ad14a5553326eaf3b2365b73162c6a24 (diff) | |
| download | bcm5719-llvm-9c916584ba198dfcd21cea645ac1406e399e5b30.tar.gz bcm5719-llvm-9c916584ba198dfcd21cea645ac1406e399e5b30.zip | |
[PPC] Avoid non-simple MVT in STBRX optimization
PR35402 triggered this case. It bswap and stores a 48bit value, current STBRX optimization transforms it into STBRX. Unfortunately 48bit is not a simple MVT, there is no PPC instruction to support it, and it can't be automatically expanded by llvm, so caused a crash.
This patch detects the non-simple MVT and returns early.
Differential Revision: https://reviews.llvm.org/D44500
llvm-svn: 327651
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/pr35402.ll | 18 |
2 files changed, 23 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 5983bcd44dc..040a2cb0d18 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -12285,6 +12285,11 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, N->getOperand(1).getValueType() == MVT::i16 || (Subtarget.hasLDBRX() && Subtarget.isPPC64() && N->getOperand(1).getValueType() == MVT::i64))) { + // STBRX can only handle simple types. + EVT mVT = cast<StoreSDNode>(N)->getMemoryVT(); + if (mVT.isExtended()) + break; + SDValue BSwapOp = N->getOperand(1).getOperand(0); // Do an any-extend to 32-bits if this is a half-word input. if (BSwapOp.getValueType() == MVT::i16) @@ -12292,7 +12297,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, // If the type of BSWAP operand is wider than stored memory width // it need to be shifted to the right side before STBRX. - EVT mVT = cast<StoreSDNode>(N)->getMemoryVT(); if (Op1VT.bitsGT(mVT)) { int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits(); BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp, diff --git a/llvm/test/CodeGen/PowerPC/pr35402.ll b/llvm/test/CodeGen/PowerPC/pr35402.ll new file mode 100644 index 00000000000..06e6d963b13 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr35402.ll @@ -0,0 +1,18 @@ +; RUN: llc -O2 < %s | FileCheck %s +target triple = "powerpc64le-linux-gnu" + +define void @test(i8* %p, i64 %data) { +entry: + %0 = tail call i64 @llvm.bswap.i64(i64 %data) + %ptr = bitcast i8* %p to i48* + %val = trunc i64 %0 to i48 + store i48 %val, i48* %ptr, align 1 + ret void + +; CHECK: sth +; CHECK: stw +; CHECK-NOT: stdbrx + +} + +declare i64 @llvm.bswap.i64(i64) |
