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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-10-24 10:23:59 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-10-24 10:23:59 +0000 |
| commit | 9c348548331a0ab783efddc113f474f545784f0e (patch) | |
| tree | e5cf1c05db563df250d28091ce3a78241bc37253 | |
| parent | d90071429979aa23c7d493320aec56c552fc13ea (diff) | |
| download | bcm5719-llvm-9c348548331a0ab783efddc113f474f545784f0e.tar.gz bcm5719-llvm-9c348548331a0ab783efddc113f474f545784f0e.zip | |
[mips] synci microMIPS instruction definition.
Add synci to the microMIPS instruction definitions, mark the MIPS sync & synci
as not being part of microMIPS. This does not cover the sync instruction alias,
as that will be handled with a different patch. Add sync to the valid tests for
microMIPS.
Reviewers: vkalintiris
Differential Revision: https://reviews.llvm.org/D25795
llvm-svn: 284962
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrFormats.td | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips/valid.s | 4 |
4 files changed, 19 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td index 68f7fcf6481..8b595f9e6c4 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td @@ -599,6 +599,17 @@ class SYNC_FM_MM : MMArch { let Inst{5-0} = 0x3c; } +class SYNCI_FM_MM : MMArch { + bits<5> rs; + bits<16> offset; + bits<32> Inst; + + let Inst{31-26} = 0b010000; + let Inst{25-21} = 0b10000; + let Inst{20-16} = rs; + let Inst{15-0} = offset; +} + class BRK_FM_MM : MMArch { bits<10> code_1; bits<10> code_2; diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index ca0978c03bf..66c2d8bfdc7 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -927,6 +927,7 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Control Instructions def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM; + def SYNCI_MM : MMRel, SYNCI_FT<"synci">, SYNCI_FM_MM; def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM; def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM; def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index ea4a8e68b71..0c2ca67128c 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1874,10 +1874,10 @@ let DecoderNamespace = "COP3_" in { def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>, ISA_MIPS2; } -} -def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2; -def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; + def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2; + def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; +} let AdditionalPredicates = [NotInMicroMips] in { def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, ISA_MIPS2; diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s index 2178faee6ce..7fd1f572829 100644 --- a/llvm/test/MC/Mips/micromips/valid.s +++ b/llvm/test/MC/Mips/micromips/valid.s @@ -207,3 +207,7 @@ recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b] rsqrt.s $f3, $f5 # CHECK: rsqrt.s $f3, $f5 # encoding: [0x54,0x65,0x02,0x3b] rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b] +sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c] +sync 0 # CHECK: sync 0 # encoding: [0x00,0x00,0x6b,0x7c] +sync 1 # CHECK: sync 1 # encoding: [0x00,0x01,0x6b,0x7c] +synci 64($5) # CHECK: synci 64($5) # encoding: [0x42,0x00,0x00,0x40] |
