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| author | Nick Lewycky <nicholas@mxc.ca> | 2011-07-08 00:19:27 +0000 |
|---|---|---|
| committer | Nick Lewycky <nicholas@mxc.ca> | 2011-07-08 00:19:27 +0000 |
| commit | 9badf60203143ee59baa69ecd401363731b09ef5 (patch) | |
| tree | a68fbc78570579495c59c346f803e6325ed4e479 | |
| parent | 7a2a0f80de2b1a0994b85e23cb5d01c384135474 (diff) | |
| download | bcm5719-llvm-9badf60203143ee59baa69ecd401363731b09ef5.tar.gz bcm5719-llvm-9badf60203143ee59baa69ecd401363731b09ef5.zip | |
Let the inline asm 'q' constraint match float, and on 64-bit double too.
Fixes PR9602!
llvm-svn: 134665
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/inline-asm-q-regs.ll | 14 |
2 files changed, 16 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0dfc3167600..709b84c1fa2 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -12891,19 +12891,19 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, // in the normal allocation? case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. if (Subtarget->is64Bit()) { - if (VT == MVT::i32) + if (VT == MVT::i32 || VT == MVT::f32) return std::make_pair(0U, X86::GR32RegisterClass); else if (VT == MVT::i16) return std::make_pair(0U, X86::GR16RegisterClass); else if (VT == MVT::i8) return std::make_pair(0U, X86::GR8RegisterClass); - else if (VT == MVT::i64) + else if (VT == MVT::i64 || VT == MVT::f64) return std::make_pair(0U, X86::GR64RegisterClass); break; } // 32-bit fallthrough case 'Q': // Q_REGS - if (VT == MVT::i32) + if (VT == MVT::i32 || VT == MVT::f32) return std::make_pair(0U, X86::GR32_ABCDRegisterClass); else if (VT == MVT::i16) return std::make_pair(0U, X86::GR16_ABCDRegisterClass); diff --git a/llvm/test/CodeGen/X86/inline-asm-q-regs.ll b/llvm/test/CodeGen/X86/inline-asm-q-regs.ll index 321fd30dbbf..1c8e2f9eec8 100644 --- a/llvm/test/CodeGen/X86/inline-asm-q-regs.ll +++ b/llvm/test/CodeGen/X86/inline-asm-q-regs.ll @@ -3,8 +3,20 @@ %0 = type { i64, i64, i64, i64, i64 } ; type %0 -define void @t() nounwind { +define void @test1() nounwind { entry: %asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0] ret void } + +; PR9602 +define void @test2(float %tmp) nounwind { + call void asm sideeffect "$0", "q"(float %tmp) nounwind + call void asm sideeffect "$0", "Q"(float %tmp) nounwind + ret void +} + +define void @test3(double %tmp) nounwind { + call void asm sideeffect "$0", "q"(double %tmp) nounwind + ret void +} |
