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| author | Javed Absar <javed.absar@arm.com> | 2015-06-26 12:14:56 +0000 |
|---|---|---|
| committer | Javed Absar <javed.absar@arm.com> | 2015-06-26 12:14:56 +0000 |
| commit | 99a9343ae6b9244b8933cef099e6fff70610f59b (patch) | |
| tree | 5bdee7fce3bef6b4959a1d7f629be6ef6f3b7691 | |
| parent | f54bb7743a5e0a0242b3d577a997cab4100c5137 (diff) | |
| download | bcm5719-llvm-99a9343ae6b9244b8933cef099e6fff70610f59b.tar.gz bcm5719-llvm-99a9343ae6b9244b8933cef099e6fff70610f59b.zip | |
[ARM] Cortex-R4F is not VFPOnlySP
Cortex-R4F TRM states that fpu supports both single and double precision.
This patch corrects the information in ARM.td file and corresponding test.
Reviewers: rengolin
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10763
llvm-svn: 240776
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/build-attributes.ll | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index c7ea18a17fe..ff12b36a0ea 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -410,7 +410,7 @@ def : ProcessorModel<"cortex-r4", CortexA8Model, def : ProcessorModel<"cortex-r4f", CortexA8Model, [ProcR4, FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, - FeatureVFP3, FeatureVFPOnlySP, FeatureD16]>; + FeatureVFP3, FeatureD16]>; // FIXME: R5 has currently the same ProcessorModel as A8. def : ProcessorModel<"cortex-r5", CortexA8Model, diff --git a/llvm/test/CodeGen/ARM/build-attributes.ll b/llvm/test/CodeGen/ARM/build-attributes.ll index 0cc4f230f28..69f02c0a86d 100644 --- a/llvm/test/CodeGen/ARM/build-attributes.ll +++ b/llvm/test/CodeGen/ARM/build-attributes.ll @@ -1049,7 +1049,7 @@ ; CORTEX-R4F: .eabi_attribute 23, 3 ; CORTEX-R4F: .eabi_attribute 24, 1 ; CORTEX-R4F: .eabi_attribute 25, 1 -; CORTEX-R4F: .eabi_attribute 27, 1 +; CORTEX-R4F-NOT: .eabi_attribute 27, 1 ; CORTEX-R4F-NOT: .eabi_attribute 28 ; CORTEX-R4F-NOT: .eabi_attribute 36 ; CORTEX-R4F: .eabi_attribute 38, 1 |
