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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-23 21:00:12 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-23 21:00:12 +0000 |
| commit | 997a9abf4cf1c9143f344b530673e78b72e3558f (patch) | |
| tree | ed7e1a94764993b777f9125d4c3b3dc65053b504 | |
| parent | dd0cb2a3e5ea2771ea4bac7b221f8188f78d0d50 (diff) | |
| download | bcm5719-llvm-997a9abf4cf1c9143f344b530673e78b72e3558f.tar.gz bcm5719-llvm-997a9abf4cf1c9143f344b530673e78b72e3558f.zip | |
AMDGPU: Fix not setting kill flag on temp reg when spilling
llvm-svn: 287808
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 71c1ac7ffbc..fb42130767a 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -477,7 +477,7 @@ void SIRegisterInfo::buildSpillLoadStore(MachineBasicBlock::iterator MI, EltSize, MinAlign(Align, EltSize * i)); auto MIB = BuildMI(*MBB, MI, DL, Desc) - .addReg(SubReg, getDefRegState(!IsStore)) + .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)) .addReg(ScratchRsrcReg) .addReg(SOffset, SOffsetRegState) .addImm(Offset) |
