diff options
author | Roman Lebedev <lebedev.ri@gmail.com> | 2019-10-21 08:21:54 +0000 |
---|---|---|
committer | Roman Lebedev <lebedev.ri@gmail.com> | 2019-10-21 08:21:54 +0000 |
commit | 9948fac6c1fae87b31a35afa84fcdb118b671c43 (patch) | |
tree | 141fe13a11811ef290369c4ebee5d57953afd003 | |
parent | 292771627735a0d23ba3e82b04f9571def812917 (diff) | |
download | bcm5719-llvm-9948fac6c1fae87b31a35afa84fcdb118b671c43.tar.gz bcm5719-llvm-9948fac6c1fae87b31a35afa84fcdb118b671c43.zip |
[NFC][InstCombine] Fixup comments
As noted in post-commit review of rL375378375378.
llvm-svn: 375397
-rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index 77907cc995d..8bc34825f8a 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -1103,7 +1103,7 @@ InstCombiner::canonicalizeCondSignextOfHighBitExtractToSignextHighBitExtract( assert((I.getOpcode() == Instruction::Add || I.getOpcode() == Instruction::Or || I.getOpcode() == Instruction::Sub) && - "Expecting add/sub instruction"); + "Expecting add/or/sub instruction"); // We have a subtraction/addition between a (potentially truncated) *logical* // right-shift of X and a "select". @@ -1158,7 +1158,7 @@ InstCombiner::canonicalizeCondSignextOfHighBitExtractToSignextHighBitExtract( const APInt *Thr; Value *SignExtendingValue, *Zero; bool ShouldSignext; - // It must be a select between two values we will later estabilish to be a + // It must be a select between two values we will later establish to be a // sign-extending value and a zero constant. The condition guarding the // sign-extension must be based on a sign bit of the same X we had in `lshr`. if (!match(Select, m_Select(m_ICmp(Pred, m_Specific(X), m_APInt(Thr)), |